Gate-to-Source/Drain FEOL Contact for Self-Aligned Multi-Gate Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing connection methods between gate structures and source/drain features in multi-gate devices require additional lithography steps and space, increasing manufacturing costs and complexity, particularly due to the use of non-self-aligned butted contacts.
Innovation Solution
A semiconductor structure with an FEOL contact structure that connects a source/drain feature of one transistor to a gate structure of another transistor, using a cladding layer deposited over a fin-shaped structure, allowing self-aligned exposure of source/drain features and direct electrical coupling with a gate electrode layer, thereby eliminating the need for MEOL or BEOL contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional butted contacts are used to connect gate structure to source/drain feature, then electrical connection is achieved, but additional lithography steps and space are required, increasing manufacturing complexity and cost
Solution Approach 1:
The gate electrode is merged with the source/drain feature through direct physical contact, eliminating the need for separate butted contact structures. The gate electrode extends to directly touch the source/drain region, combining two previously separate electrical connection paths into one integrated structure.
Solution Approach 2:
The gate electrode is positioned and formed in advance during FEOL processing to directly contact the source/drain feature before subsequent manufacturing steps. This preliminary positioning eliminates the need for later alignment and contact formation steps that would otherwise be required.
2Reliability
If butted contacts are used for gate-to-source/drain connection, then electrical coupling is established, but additional photolithography processes are needed, increasing manufacturing cost
Solution Approach 1:
The manufacturing process merges the gate electrode formation with the source/drain feature integration into a single FEOL step, eliminating the need for separate MEOL or BEOL contact formation processes. This reduces the total number of lithography steps required.
Solution Approach 2:
The gate electrode is preliminarily formed with the correct geometry and position during front-end-of-line processing, ensuring direct contact with the source/drain feature is achieved before subsequent manufacturing steps. This preliminary action eliminates the need for additional alignment and contact formation lithography steps.
3Reliability
If non-self-aligned butted contacts are used, then gate-to-source/drain connection is achieved, but space is consumed in metal line layer, impacting routing
Solution Approach 1:
The gate electrode and source/drain feature are merged into a single continuous electrical path without requiring separate contact structures in the metal line layer. This eliminates the space that would otherwise be occupied by butted contacts, freeing up routing area.
Solution Approach 2:
The connection is achieved by extending the gate electrode in the planar dimension to directly contact the source/drain feature, rather than using vertical through-silicon vias or stacked contact structures. This dimensional approach eliminates the need for additional metal line layer space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces manufacturing complexity and cost by enabling self-aligned connections at the FEOL level, improving routing efficiency and reducing the need for additional photolithography processes.
Implementation Method 1
depositing a cladding layer over the stack portion
Implementation Method 2
depositing a gate electrode layer over the upper portion of the end surface to be in direct contact with the source/drain feature
Data Source
AI summary
A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.


