FEOL Interconnect Structure for Backside Access in Ultra-Thin Die Stacks
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Solution Overview
Problem
Conventional semiconductor device fabrication methods require extensive processing time and complex operations for forming backside interconnects, limiting design flexibility and efficiency in vertical die stack assemblies.
Innovation Solution
The technology involves forming pre-positioned front-end-of-line interconnect structures during FEOL processing at or near the active side of the die, which can be accessed during BEOL or post-probe processing, eliminating the need for BEOL TSVs and enabling ultra-thin die stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional BEOL processing methods are used to form backside interconnects, then electrical connections can be established, but processing time is extensive and fabrication operations are complex
Solution Approach 1:
The patent applies preliminary action by forming interconnect structures during FEOL processing (front-end-of-line) before the typical BEOL stage. Specifically, conductive plugs are formed in trenches at the front end, and additional conductive material is deposited to create interconnect structures that extend to the backside of the die. This preliminary formation of interconnects during FEOL eliminates the need for extensive BEOL processing operations later, directly reducing processing time and fabrication complexity.
2Adaptability or versatility
If conventional BEOL processing is used, then interconnects can be formed, but design options for routing configurations are limited
Solution Approach 1:
The patent applies dimensionality change by creating three-dimensional interconnect structures that extend from the frontside through the bulk of the die to the backside. The conductive plugs and conductive material form vertical and lateral pathways that provide multiple routing dimensions. This enables flexible routing configurations by allowing signals to travel through the bulk of the die in multiple directions, significantly increasing design options for routing compared to conventional planar BEOL interconnects.
3Productivity
If FEOL processing is used to form pre-positioned interconnect structures, then processing time and complexity are reduced, but the interconnect structures must be accessible during BEOL or post-probe processing
Solution Approach 1:
The patent applies the nested doll principle by creating interconnect structures that are embedded within the die structure itself. The conductive plugs are formed in trenches that extend into the die, and conductive material is deposited to create nested layers of interconnect structures. These pre-positioned structures remain embedded within the die during BEOL processing and are subsequently accessed by forming openings through the backside dielectric material, allowing the nested structures to serve both FEOL and BEOL stages without interfering with processing operations.
Data Source
AI summary
Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.