FEOL Interconnect Capacitors Over Fins for High Density
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Solution Overview
Problem
Modern semiconductor processing faces challenges in achieving high capacitance while adhering to strict polysilicon (PC) density rules, as excessive density can lead to defects and inadequate capacitance due to native capacitance limitations between gate material and fins.
Innovation Solution
Replacing selected gates with front-end-of-line (FEOL) interconnects over fins, forming capacitors at intersections with fins, and using a low-k dielectric material to reduce gate material density while maintaining high capacitance, thus avoiding design rule violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate material density is increased to provide sufficient capacitance, then capacitance is improved, but polysilicon density rules are violated causing defects
Solution Approach 1:
The patent introduces FEOL interconnects as intermediary elements that form capacitors with the fins, replacing the need for high-density gate material. The interconnects act as a mediator between the fins and the capacitance requirement, allowing capacitance to be achieved through the interconnect-fin capacitor structure rather than through increased gate material density.
Solution Approach 2:
The patent changes the material parameter from gate material (polysilicon or high-k dielectric) to FEOL interconnect material. This parameter change allows the formation of capacitors using the interconnect layer, which has different electrical properties and can provide the required capacitance without violating polysilicon density rules.
2Reliability
If gate material density is reduced to meet design rules, then design rule compliance is improved, but capacitance becomes insufficient
Solution Approach 1:
The FEOL interconnects serve as intermediary elements that compensate for reduced gate material density. By forming capacitors between the interconnects and fins, the system maintains sufficient total capacitance even when gate material density is reduced to meet design rules.
Solution Approach 2:
The patent transitions from relying on gate material capacitance (one dimension) to utilizing interconnect-fin capacitor structures (adding another dimensional aspect). This dimensional change allows capacitance to be achieved through a different structural configuration rather than through gate material density.
3Device complexity
If native capacitance between gate material and fins is used, then device structure is simple, but capacitance is limited and insufficient for high-performance devices
Solution Approach 1:
The patent merges the interconnect layer with the capacitor formation process. By combining the FEOL interconnect structure with the fin structure to form interconnect-fin capacitors, the design achieves enhanced capacitance without adding separate, complex capacitor structures, thus maintaining relative structural simplicity while improving capacitance.
Solution Approach 2:
The FEOL interconnects serve multiple functions: they provide electrical connectivity and simultaneously form capacitors with the fins. This multi-functionality allows the same structural element to address both interconnection and capacitance requirements, reducing the need for additional dedicated capacitor structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high capacitance while meeting PC density rules, reducing defects and ensuring compliance with design specifications by utilizing FEOL interconnects and dielectric materials to form capacitors, thereby enhancing semiconductor device performance.
Implementation Method 1
forming capacitors at intersections with fins
Implementation Method 2
using a low-k dielectric material to reduce gate material density while maintaining high capacitance
Data Source
AI summary
Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins.