FEOL TFT-CMOS Integration Using Shared Gate Dielectric Layers
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Solution Overview
Problem
The integration of high-power, high-frequency, and high-speed thin-film transistors (TFT) devices into traditional CMOS logic processes is challenging due to complexity and cost, necessitating a simplified approach to reduce overall process steps and manufacturing costs.
Innovation Solution
A semiconductor structure and manufacturing method that integrates high-voltage TFT devices into the front-end-of-line (FEOL) of the CMOS logic process, defining active areas before CMOS logic device formation, using a substrate with a TFT channel layer, MOSFET, and interlayer dielectric layers functioning as a gate dielectric, and forming TFT devices in a self-aligned and coplanar manner with CMOS transistors to control thermal budget and reduce process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-power, high-frequency, and high-speed thin-film transistor (TFT) devices are integrated into traditional CMOS logic processes, then device performance and functionality are improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent merges TFT device fabrication with CMOS logic process by integrating TFT active area definition, channel layer formation, and gate electrode creation into the existing CMOS front-end-of-line process steps. The TFT channel layer is formed simultaneously with CMOS transistor channels, and TFT gates are created using the same polysilicon deposition and patterning steps as CMOS gates, thereby reducing process complexity while maintaining device performance
Solution Approach 2:
The patent employs universal process steps that serve multiple functions: the same interlayer dielectric layers function as both TFT gate dielectrics and CMOS isolation structures, the same polysilicon deposition creates both TFT gates and CMOS gates, and the same photolithography patterns define both TFT active areas and CMOS transistor regions, thereby simplifying the overall manufacturing process
2Ease of manufacture
If TFT devices are integrated into CMOS logic process, then manufacturing cost is reduced through process simplification, but thermal budget control becomes more challenging
Solution Approach 1:
The patent performs preliminary actions by defining TFT active areas before CMOS well formation and forming the TFT channel layer before CMOS transistor fabrication. This sequencing allows thermal processes to be optimized early in the workflow, enabling better thermal budget control while maintaining cost-effective manufacturing through process integration
3Temperature
If TFT active areas are defined before CMOS logic device formation, then thermal budget is controlled effectively, but process sequencing complexity increases
Solution Approach 1:
The patent merges TFT and CMOS process sequencing by combining active area definition with CMOS transistor region patterning, forming channel layers for both device types in the same epitaxial growth step, and creating gates for both TFT and CMOS transistors using identical polysilicon deposition and patterning sequences, thereby simplifying process sequencing while maintaining thermal budget control
Data Source
AI summary
The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.