FEOL TSV Structure With Pre-Etched Trench for Faster Via Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for forming through semiconductor-on-substrate vias (TSVs) in integrated circuit (IC) chips face challenges such as long etch times, high costs due to multiple photoresist masks, and a high likelihood of void formation, which degrade the performance and yield of the TSVs due to thick interlayer dielectric (ILD) and intermetal dielectric (IMD) layers.
Innovation Solution
The method involves forming a FEOL TSV by etching a trench through the FEOL layer and semiconductor layer before depositing the ILD and IMD layers, reducing the etch depth and aspect ratio, allowing for faster processing with a single photoresist mask and minimizing void formation, thereby enhancing manufacturing throughput and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If TSVs are formed through thick ILD and IMD layers using existing methods, then the via structure is completed, but etch time increases and processing productivity decreases
Solution Approach 1:
The patent applies preliminary action by forming the trench through the semiconductor layer and first ILD layer before depositing the second ILD layer and IMD layers. This sequence reduces the subsequent etch depth needed for TSV formation, thereby decreasing etch time and improving processing productivity while maintaining via functionality.
2Ease of manufacture
If multiple photoresist masks are used for TSV formation, then the via structure is completed, but manufacturing cost increases
Solution Approach 1:
The patent merges the trench formation step with the TSV formation process by creating the trench before depositing upper dielectric layers. This integration eliminates the need for separate photoresist mask layers that would otherwise be required for deep via formation, reducing manufacturing complexity and cost while achieving the same structural result.
3Reliability
If trenches are etched through thick ILD and IMD layers, then the via structure is completed, but void formation increases and yield decreases
Solution Approach 1:
The patent performs preliminary trench formation through the semiconductor layer and first ILD layer before depositing thicker dielectric layers. This preliminary action creates a defined pathway that reduces the aspect ratio for subsequent TSV etching, minimizing void formation and improving manufacturing precision and yield.
Solution Approach 2:
The patent changes the temporal sequence of layer deposition relative to trench formation. By depositing the second ILD layer and IMD layers after trench formation rather than before, the patent reduces the etch depth and aspect ratio parameters during TSV etching, thereby reducing void formation and improving yield.
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.