FEOL TSV Formation via Preliminary Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for forming semiconductor devices with group III-V materials face challenges such as long etch times, high costs due to multiple photoresist masks, and a high likelihood of void formation in the trench, leading to degraded performance and low yields due to the thick interlayer dielectric and intermetal dielectric layers.
Innovation Solution
The method involves forming a FEOL TSV by etching a trench through the FEOL layer and semiconductor layer before depositing the ILD layers, reducing the etch depth and aspect ratio, allowing for faster processing with a single photoresist mask and lower likelihood of voids, thereby improving manufacturing throughput and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the trench is etched through thick interlayer dielectric and intermetal dielectric layers using existing methods, then the TSV can be formed, but the etch time becomes excessively long and the aspect ratio becomes too high
Solution Approach 1:
The patent performs the trench etching operation before depositing the interlayer dielectric and intermetal dielectric layers. By etching the trench through the semiconductor layer and FEOL layer first, then subsequently depositing the dielectric layers over the pre-formed trench, the etch depth and aspect ratio are significantly reduced compared to etching through the complete stack of thick dielectric layers after deposition.
2Manufacturing precision
If multiple photoresist masks are used for etching, then the trench can be formed with proper dimensions, but the manufacturing cost increases
Solution Approach 1:
The patent performs the trench etching operation before depositing the interlayer dielectric and intermetal dielectric layers. By etching the trench through the semiconductor layer and FEOL layer first, then subsequently depositing the dielectric layers over the pre-formed trench, the etch depth and aspect ratio are significantly reduced compared to etching through the complete stack of thick dielectric layers after deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces processing time, lowers costs, and decreases the likelihood of voids, enhancing the performance and reliability of the semiconductor devices by maintaining the trench aspect ratio and reducing the risk of the TSV falling outside design specifications.
Implementation Method 1
etching a trench through the FEOL layer and semiconductor layer before depositing the ILD layers
Implementation Method 2
depositing the ILD layers
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.