FEOL TSV Structure With Early Trench Etching to Limit Voids
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Solution Overview
Problem
The existing methods for forming through semiconductor-on-substrate vias (TSVs) in integrated circuit (IC) chips face challenges such as long etch times, high costs due to multiple photoresist masks, and a high likelihood of void formation, which degrade the performance and yield of the TSVs.
Innovation Solution
The method involves forming a FEOL TSV by etching a trench through the FEOL layer and semiconductor layer before depositing the ILD and IMD layers, reducing the etch depth and aspect ratio, allowing for faster processing with a single photoresist mask and minimizing void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through semiconductor-on-substrate vias (TSVs) are formed using existing methods, then electrical connectivity is achieved, but etch time is excessively long and processing cost is high
Solution Approach 1:
The patent applies preliminary action by forming the FEOL TSV structure before completing the full interlayer dielectric stack. The trench is etched through the FEOL layer and semiconductor layer in advance, allowing the TSV to be prepared early in the manufacturing process. This reduces the overall etch time required later while maintaining TSV performance through careful control of the preliminary etching parameters.
2Manufacturing precision
If multiple photoresist masks are used for TSV formation, then precise patterning is achieved, but manufacturing cost increases
Solution Approach 1:
The patent applies universality by designing a single photoresist mask that serves multiple functions: it defines the TSV trench pattern, protects underlying layers during etching, and enables subsequent processing steps. This multi-functional mask design eliminates the need for multiple sequential masks, reducing manufacturing cost while maintaining patterning precision through optimized mask geometry and material selection.
3Length of stationary object
If deep trenches are etched for TSV formation, then complete substrate penetration is achieved, but void formation likelihood increases
Solution Approach 1:
The patent applies preliminary action by forming the TSV trench before depositing the interlayer dielectric layers. This allows the trench to be created when the structure is more accessible, enabling better control over etch uniformity and reducing the aspect ratio challenges that lead to void formation. The preliminary formation also allows for better support structures to be in place during etching.
Solution Approach 2:
The patent applies parameter changes by optimizing the etch process parameters specific to the FEOL TSV formation stage. This includes adjusting etch depth, etch rate, and trench dimensions to achieve complete substrate penetration while maintaining a manageable aspect ratio that prevents void formation. The parameters are tailored to the specific layer stack and material composition at the FEOL stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces processing time, lowers costs, and decreases the likelihood of voids, thereby enhancing the performance and yield of the FEOL TSVs by protecting the IC chip from moisture and cracks.
Implementation Method 1
The method involves forming a FEOL TSV by etching a trench through the FEOL layer and semiconductor layer before depositing the ILD and IMD layers
Implementation Method 2
etching a trench through the FEOL layer and semiconductor layer before depositing the ILD and IMD layers
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.