FEOL Interconnect Structures for Backside Access and Faster Routing
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes face challenges in reducing volume while increasing capacity and speed, particularly due to time-consuming and complex back-end-of-line processing for forming interconnects, which limits design options and requires extensive fabrication operations.
Innovation Solution
The technology involves forming pre-positioned front-end-of-line interconnect structures during FEOL processing, allowing for direct access and routing during BEOL or post-probe processing, eliminating the need for conventional BEOL interconnects and enabling ultra-thin die stacking with increased design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BEOL processing is used to form interconnects for backside electrical connections, then reliable electrical connections are achieved, but processing time increases and design flexibility is limited
Solution Approach 1:
Interconnect structures are pre-formed during FEOL processing before the probe stage, rather than being created during conventional BEOL processing. This preliminary formation of interconnect structures at the front end of the manufacturing line reduces subsequent processing time while maintaining electrical connection reliability through proper integration with the semiconductor substrate
Solution Approach 2:
The patent utilizes the backside dimension of the semiconductor substrate for interconnect formation, allowing electrical connections to be established through the substrate thickness. This dimensional approach enables routing configurations that are not constrained by traditional planar BEOL processing layers, thereby reducing processing steps while maintaining connection reliability
2Reliability
If conventional BEOL processing is used to form interconnects, then electrical connections are established, but design options for routing configurations are limited
Solution Approach 1:
By forming interconnect structures through the substrate thickness (backside routing) rather than only in planar layers, the patent enables three-dimensional routing configurations. This dimensional approach provides designers with additional routing paths and configuration options that are not available in conventional two-dimensional BEOL processing
Solution Approach 2:
Interconnect structures are pre-formed during FEOL processing with greater design freedom, allowing various routing configurations to be established before probe testing. This preliminary formation enables more versatile routing options compared to conventional BEOL processing that occurs later in the manufacturing sequence
3Reliability
If conventional BEOL processing is used, then interconnects are formed, but extensive fabrication operations are required
Solution Approach 1:
The patent merges interconnect formation operations with FEOL processing steps, combining what were previously separate BEOL and FEOL operations into an integrated process flow. This merging reduces the total number of fabrication operations required while maintaining electrical connection reliability through coordinated processing
Solution Approach 2:
Interconnect structures are pre-formed during FEOL processing before probe testing, eliminating the need for separate BEOL interconnect formation operations. This preliminary action reduces fabrication complexity by consolidating multiple processing steps into an earlier, more efficient operation sequence
Data Source
AI summary
Systems and methods for a semiconductor device having a substrate material with a trench at a front side, a conformal dielectric material over at least a portion of the front side of the substrate material and in the trench, a fill dielectric material on the conformal dielectric material in the trench, and a conductive portion formed during front-end-of-line (FEOL) processing. The conductive portion may include an FEOL interconnect via extending through the fill dielectric material and at least a portion of the conformal dielectric material and having a front side portion defining a front side electrical connection extending beyond the front side of the semiconductor substrate material and a backside portion defining an active contact surface. The conductive portion may extend across at least a portion of the conformal dielectric material and the fill dielectric material and have a backside surface defining an active contact surface.