FeRAM Cell Array With ADC for In-Memory Multi-Bit Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices struggle to meet the demands for high-speed operations and low power consumption, particularly in the context of ferroelectric random access memory (FeRAM), while also requiring advanced functionality for data manipulation beyond simple read and write operations.
Innovation Solution
A memory device incorporating a memory cell array with ferroelectric memory cells and an analog-to-digital converter (ADC) that allows for multi-bit data storage and direct performance of operations such as addition and multiplication on stored data, utilizing ferroelectric capacitors with spontaneous polarization to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FeRAM is used to provide high-speed read and write operations, then operation speed is improved, but the device lacks data manipulation functions beyond simple storage
Solution Approach 1:
The patent integrates multiple functions into a single memory device by combining FeRAM storage cells with an ADC unit. The device can perform both data storage (read/write operations) and data manipulation (analog-to-digital conversion, addition, multiplication) within the same architecture, eliminating the need for separate processing units and enabling versatile data handling while maintaining high-speed operation characteristics of FeRAM
2Quantity of substance
If multi-bit data is stored using multiple ferroelectric capacitors, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple single-bit storage functions into a single memory cell by integrating multiple ferroelectric capacitors (e.g., 4 capacitors for 4-bit data) within one cell structure. This allows multi-bit data to be stored and processed simultaneously in a single cell, reducing the number of cells needed and simplifying the overall device architecture while maintaining high storage capacity
Solution Approach 2:
The patent transitions from storing multi-bit data across multiple separate cells to storing it within a single cell by utilizing multiple capacitors in parallel or series configurations. This dimensional change in data organization allows simultaneous access to multiple bits through a single cell, reducing address complexity and improving access speed
3Loss of time
If ADC is selectively connected to bitlines for charge domain operations, then operation time is reduced, but power consumption increases
Solution Approach 1:
The patent performs analog-to-digital conversion and arithmetic operations directly in the charge domain within the ADC unit, eliminating the need to transfer data to external processors. This continuous processing within the memory device reduces operation time and enables seamless data manipulation without breaking the charge domain workflow, improving overall system efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed, low-power data operations with non-volatile characteristics, allowing for efficient multi-bit data processing and reduced operation time through direct charge domain operations.
Implementation Method 1
FeRAM utilizes ferroelectric materials with spontaneous polarization. This use of ferroelectric materials and spontaneous polarization allows FeRAM to have nonvolatile characteristics in which stored data is retained even when the power supply to a cell is interrupted.
Data Source
Figure 1
Figure 2~3
Figure 4A~4B
AI summary
A memory device (100) includes a memory cell array (110) including ferroelectric memory cells (MC), respectively disposed at intersections of wordlines (WL0-WLm) and bitlines (BL0-BLn), and an analog-to-digital converter (120) that is selectively connected to the bitlines (BL0-BLn) and that outputs a digital value corresponding to charges applied through a bitline of the bitlines (BL0-BLn). The charges correspond to a piece of multi-bit data having digits stored in a portion of the ferroelectric memory cells (MC) that are connected to the bitline.