FeRAM Reading Cycle Shortening via Bit Line Pre-Charging
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Solution Overview
Problem
Ferroelectric random access memory (FeRAM) devices have a limited reading cycle due to temporary rises in bit line potentials during the reading operation, which can lead to data corruption and necessitate additional rewriting steps, preventing further shortening of the cycle.
Innovation Solution
The implementation of a ferroelectric random access memory device configuration that includes MOS transistors and a control line to manage bit line and output line potentials, preventing capacitive coupling and allowing for the advancement of the plate line potential reduction timing, thereby shortening the reading cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the plate line potential is reduced to ground potential immediately after reading to shorten the cycle, then the reading cycle is shortened, but temporary rises in bit line potentials occur causing data corruption
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to a predetermined potential before the reading operation begins. This preparatory step ensures that when the plate line potential is subsequently reduced, the bit lines are already in a stable state that prevents temporary potential rises from causing data corruption, thus allowing the plate line to be reduced immediately without compromising data integrity.
Solution Approach 2:
The patent implements beforehand cushioning by introducing a pre-charge phase that cushions against the harmful effect of potential rises. The bit lines are pre-charged to a specific potential level before reading, which acts as a buffer or cushion that prevents the temporary potential rises during plate line reduction from reaching levels that would corrupt the data, thereby enabling shorter reading cycles without reliability loss.
2Reliability
If additional rewriting steps are added to prevent data corruption, then data integrity is maintained, but the reading cycle cannot be shortened further
Solution Approach 1:
The patent eliminates the need for additional rewriting steps by performing preliminary pre-charging of the bit lines before the reading operation. This preliminary action ensures data integrity is maintained throughout the reading cycle, removing the requirement for subsequent rewriting steps and thereby enabling the reading cycle to be shortened without compromising data integrity.
3Loss of time
If MOS transistors and control lines are added to manage potentials, then capacitive coupling is prevented and reading cycle is shortened, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the MOS transistors to perform multiple functions: they act as switches for potential management, provide pre-charge capability, and prevent capacitive coupling between different circuit nodes. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving the goals of preventing data corruption and shortening the reading cycle.
Data Source
AI summary
A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on.