3D FeRAM Memory-Compute Stack for Low-Latency AI Processing

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Solution Overview

Problem

Existing AI processor systems face challenges in reducing latency and power consumption during the training and inference processes, which are hardware-intensive activities.

Innovation Solution

The proposed solution involves a packaging technology that stacks a compute die on top of a memory die, utilizing ferroelectric random access memory (FeRAM) for improved performance. This configuration enhances data locality, reduces memory access latency, and lowers power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional memory and compute architectures are used, then device complexity is reduced, but memory access latency increases and power consumption increases

Engineering Contradiction:
Improvememory access latencyVSAvoidarchitecture complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges memory and compute functions into a single integrated device, where memory cells directly perform computational operations. This integration eliminates the need for separate memory access operations, reducing latency while consolidating device complexity into a unified architecture that operates more efficiently.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from traditional two-dimensional planar memory architectures to three-dimensional vertical stacking, where memory layers are stacked above compute layers. This dimensional change enables simultaneous memory access and computation operations, reducing latency without proportionally increasing device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Use of energy by stationary object

If traditional memory access methods are used, then device complexity is maintained, but power consumption increases

Engineering Contradiction:
Improvepower consumptionVSAvoidarchitecture complexity
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

By merging memory storage and compute operations into a single integrated structure, the patent eliminates redundant data transfer operations between separate memory and compute units. This reduces power consumption significantly while the integrated architecture manages complexity through unified control mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If memory and compute are integrated, then productivity increases, but device complexity increases

Engineering Contradiction:
ImproveAI processing throughputVSAvoidintegration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent uses three-dimensional vertical stacking to integrate memory and compute layers, enabling high-density integration that increases AI processing throughput. The vertical architecture allows multiple operations to occur simultaneously in different layers, improving productivity while the modular layering approach manages integration complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of FeRAM in the memory die significantly accelerates matrix multiplication processes by 15 to 20 times compared to traditional methods, while also reducing power consumption and interconnect energy, thus enhancing the overall performance and efficiency of AI processing systems.

Implementation Method 1

The first die includes a ferroelectric random access memory (FeRAM) having bit-cells, wherein each bit-cell includes an access transistor and a capacitor including ferroelectric material

Methodology Applied
Scientific EffectFerroelectric effect:

Data Source

PatentUS20250201778A1Three-dimensional stack of heterogeneous memory and compute dies
Publication Date: 2025.06.19 KEPLER COMPUTING INC
  • US20250201778A1 patent drawing
  • US20250201778A1 patent drawing
  • US20250201778A1 patent drawing

AI summary

Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.