FeRAM Data Path Read/Write Sequencing for Power Reduction
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Solution Overview
Problem
In solid-state memory, particularly in ferroelectric random-access memory (FeRAM), the reduction of chip area through time-multiplexed data communication on internal buses leads to increased power consumption, which is a concern for mobile and implantable devices where both low power consumption and minimal chip area are essential.
Innovation Solution
Implementing a memory architecture with two banks of sense amplifiers that alternate in forwarding data to an internal data bus, allowing the bus to float at its previous read state during write operations, thereby minimizing power consumption without increasing chip area, and incorporating error correction coding compatible with multiple row address sectors and column segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If time-multiplexed data communication is used on internal buses to reduce chip area, then chip area is reduced, but power consumption increases
Solution Approach 1:
The patent divides the memory array into multiple banks (e.g., Bank 0 and Bank 1) with separate sense amplifier banks. Each bank can be independently accessed, allowing the internal data bus to remain in a high-impedance state when only one bank is active, thereby reducing switching power consumption while maintaining the time-multiplexed bus structure for chip area reduction
Solution Approach 2:
The patent implements dynamic control of the internal data bus impedance state. The bus transitions between active driving states (when data transfer is needed) and high-impedance floating states (when banks are alternately accessed), optimizing power consumption based on the operational phase while preserving the area-efficient time-multiplexed architecture
2Quantity of substance
If page mode access with row-wide ECC is implemented, then fewer ECC code bits are needed, but internal bus width must be reduced through time-multiplexing
Solution Approach 1:
The patent segments the memory into banks that can be accessed independently in page mode. Each bank contains complete row data with row-wide ECC, allowing the narrow time-multiplexed internal bus to transfer data sequentially from multiple banks while maintaining full ECC capability for each bank's data row
Solution Approach 2:
The patent employs periodic time-multiplexed access to multiple memory banks through the narrow internal data bus. Data is transferred in sequential periods from different banks, enabling the bus to handle wide data words effectively despite its limited width, while row-wide ECC operates periodically on complete row data from each bank
Data Source
AI summary
A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers. The internal bus is then driven with the data to be written to the first group of columns in the row, and latched into the first bank of sense amplifiers. To the extent that the data in the second group of columns does not change from the read to write operations, power consumption otherwise necessary for switching the internal bus is avoided.