1T-1C FeRAM Fin Structure for Higher Density Memory Tuning
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Solution Overview
Problem
Current ferroelectric random access memory (FeRAM) structures have limited tuning capability and integration density, hindering their performance and flexibility.
Innovation Solution
A 1T-1C FeRAM device is formed by creating a layer stack with alternating semiconductor materials, forming nanostructures, and coupling a ferroelectric capacitor to a metal gate structure, allowing for adjustable channel region areas and enhanced threshold voltage shift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FeRAM structures are used, then manufacturing simplicity is maintained, but tuning capability and integration density are limited
Solution Approach 1:
The device is segmented into distinct functional regions: a FinFET portion with gate structure wrapping around a semiconductor fin, and a ferroelectric capacitor portion with bottom electrode, ferroelectric layer, and top electrode. This segmentation allows independent optimization of each component's properties while maintaining overall device functionality, thereby enhancing tuning capability without excessive complexity
Solution Approach 2:
The gate structure wraps around three sides of the semiconductor fin in a vertical dimension, creating a tri-gate FinFET structure. This dimensional transition from planar to vertical gating increases the effective channel width and improves gate controllability, enabling better tuning of device characteristics while maintaining compact footprint
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision requirements increase
Solution Approach 1:
The invention transitions to vertical device architecture where the gate wraps around the fin structure in the vertical dimension. This allows integration density improvement through increased vertical utilization rather than further lateral scaling, thereby reducing the stringent requirements for lateral feature size control while maintaining high component density
Solution Approach 2:
The gate structure is nested around the semiconductor fin, with the gate wrapping around three sides of the fin. This nested configuration maximizes the use of vertical space and allows multiple functional layers to be stacked, improving integration density without proportionally increasing manufacturing precision requirements
3Reliability
If gate-all-around FET devices are used, then gate controllability and current ratio are improved, but device complexity increases
Solution Approach 1:
The invention merges the FinFET structure with a ferroelectric capacitor in a integrated 1T-1C memory cell architecture. The gate structure serves dual purposes: controlling the FinFET channel and interfacing with the ferroelectric capacitor. This merging achieves high current ratio and non-volatile memory functionality while avoiding the complexity of completely separate structures
Solution Approach 2:
The gate structure and underlying fin structure serve multiple functions: they form the channel region for charge carrier control, provide the interface for ferroelectric capacitor coupling, and enable both volatile and non-volatile memory operations. This multi-functionality achieves superior current ratio and reliability without proportionally increasing structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the threshold voltage shift and improves read operation tolerance for device variations, enabling higher integration density and flexibility.
Implementation Method 1
a ferroelectric layer formed over the bottom electrode
Data Source
AI summary
A method of forming a semiconductor device includes: forming a first fin protruding above a substrate; forming first source/drain regions over the first fin; forming a first plurality of nanostructures over the first fin between the first source/drain regions; forming a first gate structure around the first plurality of nanostructures; and forming a first ferroelectric capacitor over and electrically coupled to the first gate structure.