3D FeRAM Gate Trench Structure With Inner Spacers for Faster Arrays
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing the density of Ferroelectric RAM (FeRAM) cells, which is essential for next-generation non-volatile memory due to the complexity and cost associated with scaling down processes, while maintaining high operating speed and efficiency.
Innovation Solution
A 3D FeRAM structure is developed with multiple layers of 2D arrays of single-channel FeRAM cells stacked vertically, where each layer shares common electrodes and dielectric inner spacers are used to reduce coupling capacitance, simplifying the fabrication process and enhancing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If scaling down process is used to increase FeRAM cell density, then functional density increases, but processing complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from 2D planar FeRAM cell arrangement to 3D vertical stacking architecture. Multiple FeRAM cell layers are stacked vertically with shared electrode structures, enabling density multiplication without proportionally increasing lateral footprint or processing steps. This dimensional transition allows higher cell density while maintaining manageable fabrication complexity.
2Quantity of substance
If scaling down process is used to increase FeRAM cell density, then functional density increases, but manufacturing cost increases
Solution Approach 1:
The patent implements shared electrode structures where single electrodes serve multiple FeRAM cells across different layers. Word lines, bit lines, and source/drain electrodes are shared among vertically stacked cells, reducing the total number of electrodes required. This merging approach decreases material consumption, simplifies fabrication processes, and lowers manufacturing costs while achieving higher density.
3Ease of manufacture
If conventional FeRAM structure is used, then fabrication is straightforward, but operating speed is limited by coupling capacitance
Solution Approach 1:
The patent introduces dielectric inner spacers as intermediary elements positioned between the gate electrode and source/drain electrodes. These spacers act as mediators that reduce parasitic coupling capacitance between adjacent electrodes. By inserting this dielectric layer, the patent achieves faster operating speeds through reduced capacitive coupling while maintaining a fabrication process that builds upon conventional structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density FeRAM memory arrays with simplified fabrication and increased operating speed by reducing coupling capacitance between gate and source/drain electrodes, addressing the need for higher density and efficiency in FeRAM technology.
Implementation Method 1
dielectric inner spacers are used to reduce coupling capacitance
Implementation Method 2
a ferroelectric (FE) layer surrounding the channel portions
Data Source
AI summary
A method includes forming a stack of multi-layers, each multi-layer including a first isolation layer, a semiconductor layer, and a first metal layer; etching the stack of multi-layers to form gate trenches in a channel region; removing the first isolation layers and the first metal layers from the channel region, resulting in channel portions of the semiconductor layers exposed in the gate trenches; laterally recessing the first metal layers from the gate trenches, resulting in gaps between adjacent layers of the first isolation layers and the semiconductor layers; forming an inner spacer layer in the gaps; forming a ferroelectric (FE) layer surrounding each of the channel portions and over sidewalls of the gate trenches, wherein the inner spacer layer is disposed laterally between the FE layer and the first metal layers; and depositing a metal gate layer over the FE layer and filling the gate trenches.