FeRAM Cell Layout Using Low-k Isolation to Mitigate Disturb

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Solution Overview

Problem

In memory devices, particularly ferroelectric RAM (FeRAM), the close proximity of bottom electrodes in memory cells increases the risk of disturb voltage, which can affect data stored in adjacent cells, necessitating a separation distance of at least ten nanometers when using high-k dielectrics, but this constraint is relaxed by using low-k materials with a dielectric constant less than or equal to 3.5 to reduce process tolerances and prevent disturb issues.

Innovation Solution

The integration of a low-k material with a dielectric constant less than silicon dioxide between the bottom electrodes of adjacent memory cells allows for a reduced separation distance of less than ten nanometers, effectively reducing the risk of disturb voltage and enhancing process tolerances without compromising the electrical isolation, achieved through specific processing steps involving etching and low-k material deposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-k dielectrics are used to separate bottom electrodes, then electrical isolation is improved, but the separation distance must be at least ten nanometers which increases device area and reduces manufacturing precision

Engineering Contradiction:
Improveelectrical isolationVSAvoidseparation distance tolerance
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the dielectric constant parameter of the material used for separation. By using low-k dielectric materials (k ≤ 3.5) instead of high-k dielectric materials, the patent achieves adequate electrical isolation at reduced separation distances of less than ten nanometers, thereby improving manufacturing precision while maintaining reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures combining low-k dielectric materials with the bottom electrode structures. This composite approach enables effective electrical isolation between adjacent memory cells at reduced separation distances, resolving the contradiction between maintaining isolation and achieving precise manufacturing

Inventive Principle:
Principle #40Composite materials

2Area of stationary object

If bottom electrodes are placed closer together to reduce device area, then area efficiency is improved, but the risk of disturb voltage affecting adjacent cells increases

Engineering Contradiction:
Improvememory cell areaVSAvoiddisturb voltage
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces low-k dielectric materials as intermediary substances between adjacent bottom electrodes. These materials act as mediators that provide electrical isolation even when electrodes are placed at reduced separation distances, enabling closer spacing without increasing disturb voltage risk

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By changing the dielectric parameter (dielectric constant) to low-k values (k ≤ 3.5), the patent enables reduced separation distances while maintaining adequate electrical isolation, thus allowing closer electrode placement without increasing disturb voltage effects on adjacent cells

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively decreases the disturb risk for adjacent memory cells by allowing closer electrode spacing while maintaining adequate electrical isolation, thereby improving memory device performance and manufacturing tolerances without the need for additional lithographic masks.

Implementation Method 1

a low-k dielectric material separating the first bottom electrode from the second bottom electrode

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS20240292630A1Memory devices having adjacent memory cells with mitigated disturb risk
Publication Date: 2024.08.29 MICRON TECHNOLOGY INC
  • US20240292630A1 patent drawing
  • US20240292630A1 patent drawing
  • US20240292630A1 patent drawing

AI summary

A variety of applications can include apparatus having a memory device with ferroelectric capacitors as storage structures in memory cells. The ferroelectric capacitors can be arranged vertically from a region of access transistors of the memory cells with the bottom electrodes of the ferroelectric capacitors arranged above and coupled to the access transistors. The bottom electrodes can be separated from the top electrodes of the ferroelectric capacitors by ferroelectric material. The bottom electrodes of ferroelectric capacitors of adjacent memory cells can be separated by a low-k dielectric material.