FeRAM Backup Controller for NAND Write Speed

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Solution Overview

Problem

NAND flash memory systems face limitations in writing speed due to the need for data backup during writing operations, especially when errors occur, leading to inefficiencies in SSD performance.

Innovation Solution

A memory system that uses a ferroelectric random access memory (FeRAM) to temporarily store user data, allowing for efficient data copying and invalidation processing, where user data is left in FeRAM as backup data during writing, eliminating the need for exclusive backup storage and reducing writing speed falls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is written in the NAND memory via the RAM with backup operations, then data reliability is improved, but writing speed deteriorates

Engineering Contradiction:
Improvedata reliabilityVSAvoidwriting speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent performs preliminary actions by validating the NAND memory block before writing data and preparing backup locations in advance. The controller checks whether the target block is valid and prepares backup blocks before the actual write operation, preventing the need for time-consuming error handling during data writing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary validation mechanism that acts as a mediator between the write operation and the NAND memory. The controller performs preliminary validation and uses a validation flag to indicate whether the block is ready for writing, separating the validation process from the actual write operation to improve writing speed while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If backup operations are performed in another block, then data safety is improved, but device complexity increases

Engineering Contradiction:
Improvedata safetyVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the NAND memory blocks universal by allowing them to serve multiple functions: data storage, backup storage, and validation tracking. The same memory structure is used for both primary data and backup data, and the validation flag mechanism is applied uniformly across all blocks, eliminating the need for separate dedicated backup structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements a self-service mechanism where the NAND memory system automatically manages its own validation and backup requirements. The validation flag stored in the memory block itself indicates whether the block is valid for writing, and the system automatically selects appropriate backup locations without external intervention, reducing overall system complexity.

Inventive Principle:
Principle #25Self-service

3Speed

If validation processing is performed before writing, then writing speed is improved, but loss of time increases

Engineering Contradiction:
Improvewriting speedVSAvoidvalidation time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent performs partial validation by checking only the necessary validation flag in the target block before writing, rather than performing comprehensive validation of the entire memory system. This selective validation approach provides sufficient assurance for writing speed improvement while minimizing the time lost to validation processing.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8650373B2Memory system, controller, and data transfer method
Publication Date: 2014.02.11 KIOXIA CORP
  • US8650373B2 patent drawing
  • US8650373B2 patent drawing
  • US8650373B2 patent drawing

AI summary

According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n≧2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data.