FeRAM Intervening Oxide Structure for Memory Window and Endurance
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Solution Overview
Problem
Ferroelectric random-access memory (FeRAM) devices with oxide semiconductor channel regions face reduced memory window and endurance due to limited charge carrier accumulation, leading to reduced performance and reliability.
Innovation Solution
An ultra-thin intervening structure is introduced between the ferroelectric layer and the channel layer, comprising a tri-layered, bi-layered, or single-layered oxide structure, which reduces charge trapping and improves interface engineering, enhancing device performance and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an oxide semiconductor channel region is used in FeRAM devices, then the device structure is simplified and CMOS compatibility is improved, but the memory window and endurance are reduced due to limited charge carrier accumulation
Solution Approach 1:
A charge accumulation layer is introduced as an intermediary between the oxide semiconductor channel region and the ferroelectric layer. This intermediate layer serves as a mediator to accumulate charge carriers, thereby enhancing the memory window without compromising the CMOS-compatible oxide semiconductor structure. The charge accumulation layer effectively bridges the gap between the limited charge carrier capacity of oxide semiconductors and the requirements for large memory window in FeRAM devices.
2Ease of manufacture
If an oxide semiconductor channel region is used in FeRAM devices, then the device structure is simplified and CMOS compatibility is improved, but the endurance is reduced due to limited charge carrier accumulation
Solution Approach 1:
The charge accumulation layer acts as a mediator that protects the oxide semiconductor channel from degradation during repeated write/erase cycles. By accumulating charge carriers in this intermediate layer, the stress on the oxide semiconductor and ferroelectric interface is reduced, thereby extending the operational lifetime and endurance of the device while maintaining CMOS compatibility.
3Reliability
If a thicker charge accumulation layer is used to increase charge carrier accumulation, then the memory window is improved, but the device complexity and fabrication difficulty increase
Solution Approach 1:
The charge accumulation layer is designed with optimized thickness parameters and specific material composition to achieve sufficient charge carrier accumulation without excessive thickness. By carefully tuning the physical and chemical parameters of this layer, the patent achieves large memory window while keeping the additional fabrication steps minimal and the overall device structure relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ultra-thin structure effectively reduces charge trapping, improves memory window and endurance, and tunes the band diagram, resulting in enhanced performance and reliability of the FeRAM device.
Implementation Method 1
The ultra-thin structure effectively reduces charge trapping
Implementation Method 2
ferroelectric layer over the gate structure
Data Source
AI summary
A semiconductor memory structure includes a gate structure, a ferroelectric layer over the gate structure, a channel layer over the ferroelectric layer, an intervening structure between the ferroelectric layer and the channel layer, and a source structure and a drain structure separated from each other over the channel layer. A thickness of the intervening structure is less than a thickness of the channel layer and less than a thickness of the ferroelectric layer. The channel layer and the intervening structure include different materials.