FeRAM Plate Line Interconnection Architecture for Resistance Reduction
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Solution Overview
Problem
As semiconductor devices scale down, the increased resistance of metal lines and interconnects leads to conductive noise problems and data error rates, particularly at high signal transition rates, and existing optical proximity correction techniques may not adequately address these issues, resulting in potential FeCap depolarization and degraded integrated circuit performance.
Innovation Solution
The implementation of a reduced plate line resistance in FeRAM arrays through additional plate line interconnections in the bit line direction, including connections between adjacent plate lines and dummy memory cells, to minimize bit line capacitance and reduce negative voltage spikes during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional plate line interconnections are added in the bit line direction, then plate line resistance is reduced and negative voltage spikes are minimized, but device complexity and manufacturing complexity increase
Solution Approach 1:
The plate line interconnection structure is segmented into multiple discrete interconnection points distributed along the bit line direction, rather than using a single continuous connection. This segmentation reduces the overall resistance while maintaining manageable device complexity by breaking down the interconnection into smaller, more controllable segments.
Solution Approach 2:
Multiple plate line interconnections are merged with the existing bit line structure to form an integrated network. The interconnections are combined with dummy memory cell plate lines to create a unified low-resistance path that reduces negative voltage spikes without requiring entirely separate wiring infrastructure.
2Reliability
If plate line interconnections are added to reduce resistance, then data error rates decrease, but manufacturing precision requirements increase
Solution Approach 1:
The plate line interconnections are designed to create equipotential regions across the memory array by connecting plate lines at multiple points along the bit line direction. This equipotential design ensures that voltage remains uniform across the array during write operations, minimizing the negative voltage spikes that cause data errors, while the distributed nature of the connections provides manufacturing tolerance.
3Reliability
If plate line resistance is reduced through additional interconnections, then negative voltage spike amplitude decreases, but device area increases
Solution Approach 1:
The plate line interconnections serve multiple functions simultaneously: they reduce resistance, provide voltage reference paths, and connect to dummy memory cells for testing purposes. This multi-functionality allows the same structural elements to address multiple problems without proportionally increasing device area.
Solution Approach 2:
Additional plate line interconnections are strategically placed only in regions where they are most needed to reduce negative voltage spikes, such as at the edges of the memory array or near dummy memory cells, rather than uniformly across the entire array. This localized approach reduces resistance where critical while minimizing overall area increase.
Data Source
AI summary
An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.