Vertical FeRAM-Selector Stack for FinFET Memory Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating high-density memory devices with advanced transistor technologies, such as FinFETs, while maintaining efficient manufacturing processes and circuit functionality.
Innovation Solution
The integration of ferroelectric random access memory (FeRAM) devices with FinFETs and other active devices, utilizing a multi-layer stack structure with specific dielectric and conductive layers, and forming memory cells with resistive materials and selector layers to achieve efficient data storage and circuit connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density memory devices are integrated with advanced transistor technologies, then functional density is improved, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming the multi-layer stack structure with alternating dielectric and conductive layers, creating openings through the stack, depositing memory materials in specific regions, and forming selector layers. This segmentation allows each stage to be optimized independently while achieving high functional density
Solution Approach 2:
The patent utilizes a multi-layer vertical stack structure with alternating dielectric and conductive layers, transitioning from planar to three-dimensional integration. This vertical stacking enables higher functional density by utilizing the third dimension (height) rather than only expanding in the horizontal plane
2Quantity of substance
If multi-layer stack structure with dielectric and conductive layers is used, then data storage capability is improved, but device structure complexity increases
Solution Approach 1:
The memory structure employs nested layers where conductive layers are embedded within dielectric layers, and memory materials are deposited within openings formed through the stacked structure. This nesting approach maximizes storage capacity within a compact vertical footprint
Solution Approach 2:
The patent uses composite structures combining different dielectric materials (first and second dielectric layers) and conductive materials (first and second conductive layers) with memory materials, creating a multi-material stack that enables both high storage capability and controlled electrical properties
Data Source
AI summary
A semiconductor device includes a first conductive layer, a memory layer, a second conductive layer and a selector layer. The memory layer surrounds the first conductive layer. The second conductive layer is disposed aside the memory layer. The selector layer is disposed on the second conductive layer. A first side of the second conductive layer is covered by the memory layer, a second side of the second conductive layer is covered by the selector layer, and a third side of the second conductive layer is exposed by the selector layer.