FeRAM Transition Electrode Layout for Logic Height Matching
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Solution Overview
Problem
The integration of ferroelectric random-access memory (FeRAM) devices with logic devices on the same plane is challenging due to the difficulty in etching materials of varying thicknesses and the need for precise height matching with interconnects in adjacent logic regions, which hinders the formation of high-density memory arrays.
Innovation Solution
A method involving a multistep subtractive patterning process to decouple the thickness of the transition electrode from the insulator layer, allowing for independent tuning of the ferroelectric device height while maintaining a fixed insulator layer thickness in the logic region, using non-lead-based perovskite materials and high-selectivity etching techniques to form ferroelectric capacitors with hardmask materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ferroelectric devices are integrated with logic devices on the same plane, then device density is improved, but manufacturing complexity increases due to varying material thicknesses and etching difficulties
Solution Approach 1:
The patent divides the manufacturing process into distinct segments: first forming the insulator layer across the entire substrate, then selectively removing it in memory regions, and finally forming transition electrodes only where needed. This segmentation allows independent optimization of logic and memory region thicknesses, resolving the contradiction between high device density and manufacturing complexity.
Solution Approach 2:
The patent implements local quality by creating different structural configurations in different regions: the logic region maintains a fixed insulator layer thickness for standard interconnect height, while the memory region uses selectively removed insulator and added transition electrodes to achieve the required ferroelectric device height. This local differentiation enables high-density integration without compromising manufacturing feasibility.
2Adaptability or versatility
If the thickness of ferroelectric materials is varied to match interconnect heights, then integration with logic devices is improved, but etching precision requirements increase
Solution Approach 1:
The patent applies preliminary action by first depositing the insulator layer to a predetermined thickness across the entire substrate before any selective removal. This establishes a known reference thickness that simplifies subsequent selective etching processes, as the etching depth can be precisely controlled relative to this pre-established layer, thereby reducing etching precision requirements while maintaining integration compatibility.
3Quantity of substance
If high-density memory arrays are formed, then storage capacity is improved, but fabrication flexibility decreases due to height constraints
Solution Approach 1:
The patent resolves the height constraint issue by introducing a vertical dimension solution: instead of varying the insulator layer thickness in the horizontal plane (which would compromise fabrication flexibility), the patent adds transition electrodes vertically on top of the insulator in memory regions. This dimensional approach enables high-density storage capacity while maintaining fabrication flexibility, as the height adjustment is achieved through additive rather than subtractive processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of high-density FeRAM devices with improved manufacturability and flexibility in tuning device heights, maintaining environmental friendliness and reducing fabrication costs.
Implementation Method 1
FeRAM devices include materials that have a variety of thicknesses
Implementation Method 2
be difficult to etch
Data Source
AI summary
A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.