Ferrite Protection Liners for Through Silicon Vias in 3D Memory
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in scaling down dimensions while maintaining quality, yield, performance, and reliability, particularly in reducing electromagnetic interference (EMI) and parasitic capacitance, which are exacerbated by the complexity of down-scaling processes.
Innovation Solution
The semiconductor device incorporates protection liners made of materials like manganese-zinc ferrite, nickel-zinc ferrite, or yttrium iron garnet around through silicon vias, along with a connection structure and alleviation layers to reduce EMI and alleviate parasitic capacitance, and is fabricated using a method involving vertically stacked semiconductor memory dies connected by microbumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional through silicon via structures are used in scaled-down semiconductor devices, then manufacturing process complexity is reduced, but electromagnetic interference and parasitic capacitance increase
Solution Approach 1:
A protection liner made of ferrite material is introduced as an intermediary layer between the conductive through silicon via and the surrounding environment. This liner mediates the electromagnetic field interactions, blocking harmful EMI and reducing parasitic capacitance while maintaining the via's electrical function, thus resolving the contradiction between simple manufacturing and EMI performance.
Solution Approach 2:
The through silicon via structure is transformed from a simple conductive material into a composite structure consisting of a conductive core (copper or aluminum) surrounded by a ferrite protection liner. This composite material approach provides both electrical conductivity and electromagnetic shielding, reducing EMI and parasitic capacitance without significantly complicating the manufacturing process.
2Device complexity
If conventional through silicon via structures are used in scaled-down semiconductor devices, then manufacturing process complexity is reduced, but device performance deteriorates
Solution Approach 1:
The ferrite protection liner acts as an intermediary that shields the conductive via from electromagnetic interference, thereby improving signal integrity and device performance. The liner maintains electrical isolation while allowing thermal conduction, resolving the contradiction between manufacturing simplicity and performance reliability.
Solution Approach 2:
The composite structure of conductive core plus ferrite liner provides dual functionality: electrical conductivity for signal/power transmission and electromagnetic shielding for performance enhancement. This composite approach improves reliability without significantly increasing manufacturing complexity, as the liner can be formed using standard deposition processes.
3Object-affected harmful factors
If protection liners made of ferrite materials are added around through silicon vias, then electromagnetic interference is reduced, but manufacturing complexity increases
Solution Approach 1:
The protection liner is designed with specific parameter ranges: thickness of 10-100 nm and ferrite material composition (manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, or yttrium iron garnet). These parameter optimizations ensure effective EMI shielding while maintaining compatibility with existing semiconductor manufacturing processes, thus minimizing the increase in manufacturing complexity.
Solution Approach 2:
Instead of using complex mechanical shielding structures or post-processing EMI protection methods, the patent substitutes a thin ferrite liner deposited directly during the via formation process. This replaces potential mechanical complexity with a simple materials science solution that integrates seamlessly into the existing fabrication flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces electromagnetic interference and improves the performance of semiconductor devices by utilizing specific ferrite materials and alleviation layers to mitigate parasitic capacitance, enhancing overall device reliability and efficiency.
Implementation Method 1
a plurality of protection liners positioned on sides of the plurality of through silicon vias; wherein the plurality of protection liners are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a plurality of semiconductor memory dies vertically stacked through a plurality of microbumps; a plurality of through silicon vias positioned in the plurality of semiconductor dies and electrically coupled through the plurality of microbumps; and a plurality of protection liners positioned on sides of the plurality of through silicon vias; wherein the plurality of protection liners are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet.