Ferroelectric 2D Memory Transistor Gate Stack Design
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Solution Overview
Problem
Conventional computing systems face limitations in power consumption and performance due to issues like tunneling leakage current and high dissipated power, and existing non-volatile memory technologies, such as flash memory, require high voltages incompatible with CMOS technology, necessitating the development of novel architectures for improved data transmission rates and reduced power consumption.
Innovation Solution
The integration of two-dimensional material layers, specifically molybdenum disulfide (MoS2), with ferroelectric materials in a flexible electronics device structure, allowing for high-temperature processing without decomposition, and using a hybrid gate stack with zirconium-doped hafnium oxide and hafnium oxide layers to enhance ferroelectricity and reduce operating voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell size is shrunk to increase density, then storage capacity is improved, but tunneling leakage current increases and dissipated power increases
Solution Approach 1:
The patent transitions from conventional silicon-based three-dimensional materials to two-dimensional material layers (such as MoS2, WSe2, WS2, MoSe2, black phosphorus, and antimonene), fundamentally changing the dimensional parameter of the channel material. This parameter change enables continued scaling at advanced technology nodes while avoiding the tunneling leakage and power dissipation issues that plague conventional scaled devices.
2Quantity of substance
If flash memory is used for non-volatile storage, then storage capacity is improved, but high voltages (20V) are required for write and erase operations which are incompatible with CMOS
Solution Approach 1:
The patent employs ferroelectric materials (such as Pb(Zr1-xTix)O3 or Pb1-xLaxZr1-yTiyO3 with specific compositional ranges) in the gate dielectric layer, which enables non-volatile memory operation at low voltages compatible with standard CMOS processes. The ferroelectric polarization state provides non-volatile storage without requiring the high voltages needed by conventional flash memory.
Solution Approach 2:
The patent creates a composite structure combining two-dimensional channel materials with ferroelectric gate dielectrics. This composite material system integrates the high mobility and atomic thinness of 2D materials with the non-volatile low-voltage switching characteristics of ferroelectrics, achieving both non-volatility and CMOS compatibility simultaneously.
3Loss of energy
If two-dimensional material layers are used in memory devices, then power consumption is reduced and performance is improved, but flexibility and mechanical robustness are enhanced
Solution Approach 1:
The patent utilizes the inherent flexibility of atomically thin two-dimensional material layers to create bendable and flexible memory devices. These 2D material channels can be integrated onto flexible substrates, enabling wearable electronics and flexible computing applications while maintaining low power consumption and high performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of flexible, low-power, high-performance memory devices with efficient data storage and transmission, achieving distinct write and erase states with low-voltage operation and synaptic-like behavior, suitable for energy-efficient computing applications.
Implementation Method 1
A ferroelectric layer is provided over the buffer layer
Implementation Method 2
a two-dimensional material layer provided over a portion of a top surface of the dielectric layer
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Disclosed is a transistor device including a memory cell comprising a gate stack with sidewalls provided over a substrate. The gate stack includes a metal gate layer provided over the substrate. A buffer layer is provided over the metal gate layer, a ferroelectric layer is provided over the buffer layer, and a dielectric layer is provided over the ferroelectric layer. A two-dimensional, 2D, material layer is provided over a portion of a top surface of the dielectric layer. Source and drain regions are provided on separate portions of the top surface of the dielectric layer so as to create a cavity wherein the 2D material layer is located.