Ferroelectric Ambipolar Transistor for Reconfigurable Conductivity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional transistors are limited to either N-type or P-type conductivity, requiring separate formation and design processes, which complicates the manufacturing of circuits and reduces flexibility in channel formation.
Innovation Solution
An ambipolar transistor design featuring a back electrode with ferroelectric patterns, electrodes, and a channel part doped with both N-type and P-type channels, allowing for reconfiguration via a dipole control signal to control conductivity type, improving conduction and blocking characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate N-type and P-type transistors are formed, then each transistor has dedicated conductivity control, but the manufacturing process complexity increases and area consumption increases
Solution Approach 1:
The patent combines both N-type and P-type channel regions within a single transistor structure, allowing one transistor to perform functions that previously required separate N-type and P-type transistors. This merging reduces manufacturing process complexity and area consumption while maintaining dedicated conductivity control through the ferroelectric gate mechanism.
Solution Approach 2:
The ambipolar transistor is designed to function as both an N-type and P-type transistor depending on the polarization state of the ferroelectric gate. This multi-functionality allows a single device to replace multiple specialized transistors, simplifying the overall circuit design and manufacturing process.
2Reliability
If separate N-type and P-type transistors are formed, then each transistor has optimized conductivity characteristics, but area consumption increases
Solution Approach 1:
The patent merges N-type and P-type channel regions into a single transistor footprint, achieving both conductivity types within the same device area. This eliminates the need for separate N-type and P-type transistor instances, thereby reducing total area consumption while maintaining optimized conductivity characteristics through selective channel activation.
3Ease of manufacture
If conventional unipolar transistors are used, then the manufacturing process is simpler, but flexibility in channel formation and conductivity control is reduced
Solution Approach 1:
The patent introduces dynamic reconfigurability through the ferroelectric gate, which can switch between different polarization states to dynamically change the transistor's conductivity type. This dynamic capability provides flexibility in channel formation while maintaining compatibility with standard manufacturing processes, as the reconfigurability is achieved through electrical control rather than requiring separate fabrication steps for each transistor type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables selective reconfiguration into N and P types, enhancing conduction resistance, blocking resistance, and reducing area consumption, while simplifying the manufacturing process by using ferroelectric materials that switch polarization in response to an electric field.
Implementation Method 1
a first ferroelectric pattern and a second ferroelectric pattern located on the back electrode and spaced apart from each other
Implementation Method 2
ferroelectric materials that switch polarization in response to an electric field
Implementation Method 3
a channel part connected between the first electrode and the second electrode, and including a first channel doped with a first type and a second channel doped with a second type
Implementation Method 4
first channel doped with a first type and a second channel doped with a second type
Data Source
AI summary
An ambipolar transistor according to the embodiment includes: a back electrode; a first ferroelectric pattern and a second ferroelectric pattern located on the back electrode and spaced apart from each other; a first electrode located on the first ferroelectric pattern and a second electrode located on the second ferroelectric pattern; a channel part connected between the first electrode and the second electrode, and including a first channel doped with a first type and a second channel doped with a second type; and a gate stack located on the channel part.