Ferroelectric Capacitor Array Layout for Nanoscale Signal Measurement

The patent combines multiple nanoscale ferroelectric capacitors into an array structure where multiple capacitor plates are connected in parallel between common bit line and word line. This merging approach maintains the small footprint advantage while collectively generating sufficient electrical signal strength for effective characterization by standard semiconductor tools.

The patent creates multiple copies of the nanoscale ferroelectric capacitor structure arranged in an array format. Each capacitor plate is a copy of the basic nanoscale unit, and when activated together through the bit line and word line, they produce an amplified electrical response that can be detected by conventional characterization equipment.

The bit line and word line serve multiple functions: they individually address specific capacitor plates within the array, they can activate multiple plates simultaneously for amplified signaling, and they enable selective testing of individual or groups of capacitors. This multi-functionality reduces the need for additional complex addressing circuitry.

The patent employs dynamic control of the bit line and word line voltages to selectively activate different combinations of capacitor plates. By dynamically adjusting which lines are activated and at what voltage levels, the system can adaptively test individual capacitors or groups, providing flexibility that simplifies the overall testing architecture.