Ferroelectric Bit-Cell Cure Phase for Read Disturb Mitigation
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Solution Overview
Problem
Traditional non-volatile memory bit-cells, particularly those using ferroelectric materials, suffer from charge disturbance due to access operations, leading to polarization decay and increased leakage, which necessitates frequent refresh operations that consume power and reduce memory array availability.
Innovation Solution
Implementing a pulsing scheme with a cure phase in write and read operations for 1TnC and multi-element ferroelectric gain bit-cells, where the plate-line voltage is set to half Vdd during the cure phase to negate disturb fields on unselected capacitors, reducing the need for frequent refreshes and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to mitigate charge disturbance on capacitors, then data retention reliability is improved, but power consumption increases and memory array availability decreases
Solution Approach 1:
The patent applies preliminary action by performing a cure phase before the actual read or write operation. During this cure phase, the plate-line voltage is set to half Vdd to negate disturb fields on unselected capacitors in advance, preventing charge disturbance before it occurs. This proactive approach reduces the need for frequent refresh operations, thereby lowering power consumption while maintaining data retention reliability.
Solution Approach 2:
The patent implements preliminary anti-action by applying a counter-voltage during the cure phase that opposes and neutralizes the disturb fields that would otherwise affect unselected capacitors. By setting the plate-line voltage to half Vdd during the cure phase, the patent creates an opposing electric field that cancels out the harmful disturb fields, preventing polarization decay and charge loss before they can occur during subsequent read/write operations.
2Reliability
If frequent refresh operations are performed to mitigate charge disturbance on capacitors, then data retention reliability is improved, but memory array availability decreases
Solution Approach 1:
The patent applies preliminary action by performing a cure phase before the actual read or write operation. During this cure phase, the plate-line voltage is set to half Vdd to negate disturb fields on unselected capacitors in advance, preventing charge disturbance before it occurs. This proactive approach reduces the need for frequent refresh operations, thereby maintaining data retention reliability while improving memory array availability for servicing read and write requests.
3Duration of action of stationary object
If non-volatile memory bit-cells use ferroelectric materials, then data retention without power is improved, but charge disturbance during access operations increases
Solution Approach 1:
The patent extracts or separates the harmful disturb field effect from the normal read/write operations by introducing a distinct cure phase. During this separate phase, the plate-line voltage is specifically set to half Vdd to target and negate only the disturb fields on unselected capacitors, while leaving the selected capacitor's data intact. This separation allows the ferroelectric material to maintain its non-volatile data retention properties while eliminating the charge disturbance problem during access operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates charge disturbance, allowing for longer durations between refresh operations and reducing power consumption by eliminating time accumulative disturb errors on unselected capacitors, thereby enhancing memory endurance and efficiency.
Implementation Method 1
Some memory bit-cells of a memory array may use multiple capacitors. Read and/or write operations on a selected capacitor of a bit-cell may disturb voltage on unselected capacitors of the same bit-cell.
Implementation Method 2
Implementing a pulsing scheme with a cure phase in write and read operations for 1TnC and multi-element ferroelectric gain bit-cells, where the plate-line voltage is set to half Vdd during the cure phase to negate disturb fields on unselected capacitors
Data Source
AI summary
A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.