Ferroelectric Variable Capacitance Device With ESD Protection
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Solution Overview
Problem
Variable capacitance elements with ferroelectric films have poor Electro-Static Discharge (ESD) resistance compared to MEMS or semiconductor-based elements, limiting the reduction in film thickness for improved control sensitivity due to breakdown risks from ESD surges.
Innovation Solution
A variable capacitance device with a ferroelectric thin film and ESD protection elements integrated on a semiconductor substrate, where the ESD protection is isolated from the variable capacitance element, using a redistribution layer and electrode pads for enhanced thermal resistance and flatness, and insulating layers for increased isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the thickness of the ferroelectric film is reduced to increase control sensitivity, then the control sensitivity is improved, but the ESD resistance property is deteriorated
Solution Approach 1:
The patent divides the device into functionally independent sections: the variable capacitance element section with the ferroelectric thin film is separated from the ESD protection element section. This segmentation allows each section to be optimized independently - the ferroelectric film can be made thin for high control sensitivity while the ESD protection elements provide robust surge protection, resolving the contradiction between sensitivity and reliability
Solution Approach 2:
The patent introduces a redistribution layer as an intermediary structure between the variable capacitance element and the ESD protection element. This redistribution layer provides both electrical connection and physical isolation, allowing the thin ferroelectric film to maintain high sensitivity while the ESD protection elements handle surge currents, thus resolving the contradiction between control sensitivity and ESD resistance
2Measurement precision
If the thickness of the ferroelectric film is reduced to improve control sensitivity, then the control sensitivity is improved, but the ferroelectric film is more susceptible to breakdown from ESD surges
Solution Approach 1:
The patent implements ESD protection elements and grounding structures beforehand to cushion against ESD surges before they can damage the thin ferroelectric film. The ESD protection elements are positioned to intercept surge currents, providing preemptive protection that allows the use of thin ferroelectric films for high sensitivity without risking breakdown from ESD events
3Reliability
If ESD protection elements are integrated close to the variable capacitance element to improve ESD resistance, then the ESD resistance is improved, but the device area increases
Solution Approach 1:
The patent utilizes vertical layering (another dimension) to integrate ESD protection elements with the variable capacitance element. The ESD protection elements are formed in different layers and connected through vertical conductive paths, allowing compact three-dimensional integration that provides robust ESD protection without significantly increasing the planar device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a small, high-ESD-resistant variable capacitance device with high control sensitivity by securing isolation between the ESD protection and variable capacitance elements, ensuring reliability and thermal stability.
Implementation Method 1
variable capacitance elements whose dielectric constant is changed by application of a control voltage
Implementation Method 2
an ESD (Electro-Static Discharge) resistance property is poor
Data Source
Figure 1
Figure 2
Figure 3A~3A(4)
AI summary
There are included a semiconductor substrate (10), a redistribution layer (50) provided on a main surface of the semiconductor substrate (10), and a plurality of terminal electrodes (PE) including a first input/output terminal, a second input/output terminal, a ground terminal and a control voltage application terminal, where a variable capacitance element section (VC) that is a ferroelectric thin film is formed to the redistribution layer (50), the variable capacitance element section (VC) being formed from a pair of capacitor electrodes connected to the first input/output terminal and the second input/output terminal, respectively, and a ferroelectric thin film disposed between the pair of capacitor electrodes, and where an ESD protection element (ESDP1, ESDP2) connected between the first input/output terminal or the second input/output terminal and the ground terminal (GND) is formed on the main surface of the semiconductor substrate (10).