Multi-Threshold Voltage Control via Ferroelectric Capacitance Tuning
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Solution Overview
Problem
Current designs of both planar MOS transistors and FinFET devices are inadequate in achieving desirable multi-threshold voltages, which is essential for effective control of the channel region and current between the source and drain.
Innovation Solution
The semiconductor device incorporates a first and second metal-oxide semiconductor (MOS) transistor on a substrate, each connected to a ferroelectric (FE) layer with different capacitance, achieved through variations in area, thickness, or dielectric constant of the FE layers, allowing for distinct threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If doping implant or multi work function metal layers are used to achieve multi-threshold voltage, then threshold voltage control is attempted, but the approach is incompetent in achieving desirable threshold voltages
Solution Approach 1:
The patent applies parameter changes by utilizing ferroelectric layers with different capacitance values (achieved through variations in area, thickness, or dielectric constant) to directly control and differentiate threshold voltages of multiple MOS transistors. This approach replaces the ineffective doping implant or multi work function metal layers methodology with a capacitance-based control mechanism that successfully achieves the desired multi-threshold voltage states.
2Adaptability or versatility
If conventional means are used for achieving multi-threshold voltage in planar MOS transistors or FinFET devices, then existing structure is maintained, but effective multi-threshold voltage achievement is not realized
Solution Approach 1:
The patent utilizes parameter changes by introducing ferroelectric layers with varying capacitance characteristics (through area, thickness, or dielectric constant modifications) to enable precise threshold voltage control in MOS transistors. This successfully achieves multi-threshold voltage capability where conventional approaches failed.
3Manufacturing precision
If three-dimensional FinFET structure is used to increase channel control, then overlapping area between gate and fin increases, but conventional threshold voltage control methods become inadequate
Solution Approach 1:
The patent applies parameter changes by incorporating ferroelectric layers with different capacitance values in FinFET devices, enabling multi-threshold voltage achievement that complements the improved channel control provided by the three-dimensional FinFET structure. This overcomes the inadequacy of conventional threshold voltage control methods in FinFET technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the semiconductor device to achieve multi-threshold voltage states by adjusting the capacitance of the FE layers, thereby improving the control over the channel region and current between the source and drain, addressing the limitations of existing technologies.
Implementation Method 1
a first ferroelectric (FE) layer connected to the first MOS transistor; a second FE layer connected to the second MOS transistor. Preferably, the first FE layer and the second FE layer include different capacitance
Data Source
AI summary
A semiconductor device preferably includes: a first metal-oxide semiconductor (MOS) transistor on a substrate; a first ferroelectric (FE) layer connected to the first MOS transistor; a second MOS transistor on the substrate; and a second FE layer connected to the second MOS transistor. Preferably, the first FE layer and the second FE layer include different capacitance.