Ferroelectric Capacitor Integration in Embedded SRAM
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Solution Overview
Problem
Conventional semiconductor technologies face limitations in scaling integrated circuits due to poor density, high leakage power, and sensitivity to variation in 6T-SRAM, off-chip dense memories, and conventional eDRAM, which restricts memory capacity and performance.
Innovation Solution
The integration of ferroelectric-capacitors with a multi-metal-level (MML) interconnect structure in ultra-dense embedded SRAM devices, enabling increased on-chip cache memory size and improved performance by forming large ferroelectric capacitors while preserving density and topography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 6T-SRAM is used, then the technology is easily integratable with logic transistors, but the density is poor and cache memory size is limited
Solution Approach 1:
The patent transitions from planar 2D SRAM layout to 3D vertical architecture by stacking multiple metal layers (M1, M2, M3) and dielectric layers to form capacitors above the bitline. This vertical stacking enables increased cache memory density without increasing the footprint area, directly resolving the contradiction between memory size and unit-cell area.
2Quantity of substance
If off-chip dense memory is used, then memory size is improved, but operating speed is reduced and bandwidth is limited
Solution Approach 1:
The patent merges high-density memory capabilities with on-chip integration by incorporating large ferroelectric capacitors directly into the SRAM structure using the same CMOS fabrication process. This combination achieves both increased memory size and high operating speed by eliminating the need for separate off-chip memory packages, resolving the speed-bandwidth limitation.
3Quantity of substance
If conventional eDRAM is used, then large capacitors can be formed, but the process is challenging to scale and logic technology is affected
Solution Approach 1:
The patent creates a universal fabrication process that forms both logic transistors and large ferroelectric capacitors using the same CMOS steps. The capacitor structure utilizes existing interconnect layers (M1, M2, M3) and dielectric materials already present in the logic fabrication process, enabling large capacitors without compromising process scalability or logic technology.
4Quantity of substance
If standard 6T-SRAM is used, then the technology isๆ็ and reliable, but only small amounts of cache memory can be formed on chip area
Solution Approach 1:
The patent employs vertical stacking of multiple metal layers and dielectric layers to create a three-dimensional memory structure. This approach increases the amount of cache memory that can be formed on a given chip area by utilizing the vertical dimension, thereby improving memory density without expanding the chip footprint.
Data Source
AI summary
Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.