Ferroelectric Capacitor Layering for High-Capacitance Semiconductor Cells
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Solution Overview
Problem
As integration densities of semiconductor devices increase, there is a need for capacitors with high electrostatic capacitance in limited areas, which existing semiconductor devices fail to achieve effectively due to limitations in controlling the fine structure of dielectric layers.
Innovation Solution
A semiconductor device is designed with a capacitor structure that includes a dielectric layer comprising a combination of anti-ferroelectric and ferroelectric materials, where the thermal expansion coefficients of these layers differ, creating tensile or compressive stress to control the crystal phase and grain size, thereby maximizing electrostatic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single dielectric layer is used in the capacitor, then the device structure is simple, but the electrostatic capacitance is insufficient and fine structure control is difficult
Solution Approach 1:
The dielectric layer is segmented into multiple distinct layers: a first dielectric layer with anti-ferroelectric properties and a second dielectric layer with ferroelectric properties. This segmentation allows each layer to contribute different functional characteristics, enabling fine structure control and enhanced electrostatic capacitance while maintaining manageable device complexity through systematic layering
Solution Approach 2:
The patent employs composite dielectric materials with different crystal phases and thermal expansion coefficients. The first dielectric layer (e.g., HfZrO4) and second dielectric layer (e.g., HfO2) form a composite structure where each material's unique properties synergistically contribute to achieving high electrostatic capacitance and controllable fine structure
2Reliability
If the dielectric layer thickness is increased to increase capacitance, then the electrostatic capacitance increases, but the area available for electrode placement decreases
Solution Approach 1:
The patent changes the material parameters of the dielectric layers, specifically selecting materials with different thermal expansion coefficients and dielectric constants. By adjusting the thickness ratios and material compositions of the first and second dielectric layers, the patent achieves high electrostatic capacitance without requiring excessive total thickness, thereby preserving adequate electrode area
Solution Approach 2:
The patent utilizes phase transition properties of the dielectric materials, particularly the coexistence of tetragonal and monoclinic crystal phases. The first dielectric layer exhibits electric field-induced phase transition between anti-ferroelectric and paraelectric states, while the second layer maintains ferroelectric properties. These phase transitions enable high capacitance through field-induced polarization changes without requiring large physical dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for increased electrostatic capacitance and precise control of the dielectric layer structure, enhancing the performance of semiconductor devices by optimizing the fraction and size of crystal phases within the dielectric layers.
Implementation Method 1
A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer
Implementation Method 2
The first dielectric layer comprises an anti-ferroelectric first crystal phase, the second dielectric layer comprises a ferroelectric second crystal phase
Data Source
AI summary
A semiconductor device includes a capacitor. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes a first dielectric layer and a second dielectric layer that are interposed between the bottom electrode and the top electrode and are stacked in the first direction. The first dielectric layer is anti-ferroelectric, and the second dielectric layer is ferroelectric. A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.