Ferroelectric Capacitor Multiply-Accumulate Device for Neural Network Inference
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Solution Overview
Problem
Existing neural network circuits face challenges in holding parameters due to volatile capacitive coupling memories and limited write cycles in ferroelectric transistors, affecting the accuracy and practicality of multiply-accumulate operations.
Innovation Solution
A multiply-accumulate operation device utilizing ferroelectric capacitors, arranged in rows and columns with input and output wiring lines, allows parameters to be stored with minimal variation in load capacitance, enabling high accuracy inference and an extremely large number of rewriting cycles compared to other memory types like ReRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a parameter is stored in a volatile capacitive coupling memory, then the device complexity is reduced, but the parameter cannot be held reliably
Solution Approach 1:
The patent changes the memory type from volatile capacitive coupling to ferroelectric capacitor, utilizing the ferroelectric effect to achieve non-volatile storage while maintaining compatibility with the existing memory architecture. This parameter change in material properties enables reliable parameter holding without significantly increasing device complexity.
2Reliability
If a parameter is stored in a ferroelectric transistor, then the parameter can be held non-volatily, but the number of rewriting times is limited
Solution Approach 1:
The patent uses a separate reference cell that stores reference data independently from the main data cell. This copying approach allows the system to perform read operations on the reference cell without affecting the main stored data, thereby enabling repeated read operations and extending the effective duration of data retention without being limited by write cycle constraints.
3Adaptability or versatility
If the variation in load capacitance of cells is great, then the device can accommodate different cell configurations, but noise is generated during inference
Solution Approach 1:
The patent introduces a reference cell that provides a baseline capacitance value for comparison. By using differential sensing that compares the main cell against the reference cell, the system can compensate for variations in load capacitance and eliminate noise caused by capacitance mismatches, thereby maintaining high inference accuracy across different cell configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides high accuracy in neural network inference and practical write cycles, overcoming the limitations of volatile memories and ferroelectric transistors, while being cost-effective and area-efficient on a silicon substrate.
Implementation Method 1
Each of the multiple output wiring lines is configured to store an amount of electric charge corresponding to a product of capacitance of the ferroelectric capacitor of each of the cells and an input voltage supplied to the input wiring line
Implementation Method 2
the variation in the load capacitance of the ferroelectric capacitors that each hold the parameter (the weight) is small. It is therefore possible to perform the inference with high accuracy
Data Source
AI summary
A multiply-accumulate operation device according to an aspect of the present disclosure includes multiple cells each including a transistor and a ferroelectric capacitor that is coupled to a first source and drain terminal of the transistor. The multiple cells are arranged in rows and columns. This multiply-accumulate operation device further includes multiple input wiring lines and multiple output wiring lines. Each unit of one or more of the multiple input wiring lines is assigned to corresponding one of the rows of the multiple cells. The multiple input wiring lines are coupled to the ferroelectric capacitors. Each of the multiple output wiring lines is assigned to corresponding one of the columns of the multiple cells. The multiple output wiring lines are coupled to second source and drain terminals of the transistors. The multiple output wiring lines are each configured to store an amount of electric charge corresponding to a product of capacitance of the ferroelectric capacitor of each of the cells and an input voltage supplied to the input wiring line.