Selective Ferroelectric Capacitor Layout to Cut Parasitic Capacitance
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Solution Overview
Problem
Current ferroelectric random-access memory (FeRAM) devices face challenges in achieving denser, faster, and more reliable performance due to issues with parasitic capacitances and extraneous ferroelectric material deposition, which affects signal propagation and memory reliability.
Innovation Solution
The solution involves forming three-dimensional ferroelectric capacitors with discrete ferroelectric layers selectively deposited only on desired metal surfaces, using techniques like atomic layer deposition (ALD) and atomic layer etch (ALE) to minimize parasitic capacitances and improve manufacturing efficiency, and employing non-growth materials to prevent unwanted ferroelectric material deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ferroelectric deposition methods are used, then manufacturing simplicity is maintained, but parasitic capacitances increase and memory reliability deteriorates
Solution Approach 1:
The patent divides the deposition process into multiple selective deposition steps, where ferroelectric material is deposited only on specific metal surfaces (inner plate, outer plates, and intermediate structures) rather than uniformly across all surfaces. This segmentation approach reduces parasitic capacitances by eliminating extraneous ferroelectric material while maintaining manufacturing feasibility through controlled deposition sequences
Solution Approach 2:
The patent implements local quality by varying the deposition conditions and selectivity for different regions of the device. Different metal surfaces receive ferroelectric material with different thicknesses or presence based on their functional requirements, optimizing performance while reducing unwanted parasitic effects in non-critical areas
2Speed
If extraneous ferroelectric material is present on metal surfaces, then manufacturing process is simpler, but signal propagation deteriorates due to increased parasitic capacitances
Solution Approach 1:
The patent extracts and removes extraneous ferroelectric material from metal surfaces where it would create parasitic capacitances. This is achieved through selective deposition techniques that prevent unwanted material formation, or through targeted removal processes that eliminate excess material while preserving the functional ferroelectric layers needed for memory operation
3Manufacturing precision
If ferroelectric material is deposited on all metal surfaces, then deposition process is simpler, but device performance deteriorates due to parasitic capacitances
Solution Approach 1:
The patent applies preliminary actions by preparing metal surfaces with specific properties (such as adhesion layers or surface treatments) before deposition, and by using masking techniques or selective nucleation approaches that pre-determine where ferroelectric material will deposit. This preliminary preparation enables precise material placement without requiring complex post-deposition processing, maintaining productivity while achieving high precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory device reliability and speed by reducing parasitic capacitances, simplifying the manufacturing process, and ensuring precise ferroelectric material placement, leading to improved system performance and cost-effectiveness.
Implementation Method 1
using techniques like atomic layer deposition (ALD)
Implementation Method 2
using techniques like atomic layer deposition (ALD) and atomic layer etch (ALE)
Data Source
AI summary
A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.