Ferroelectric Capacitor Pocket Integration for Logic-Compatible FeRAM
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Solution Overview
Problem
The integration of ferroelectric random-access memory (FeRAM) devices with logic devices on the same plane is challenging due to the difficulty in etching materials of varying thicknesses and the need to target specific device thicknesses within height constraints of interconnects in adjacent logic regions, requiring alternative methods for patterning and forming devices with ferroelectric materials to achieve high-density arrays.
Innovation Solution
A method involving a multistep subtractive patterning process where a ferroelectric capacitor is formed on conductive interconnects in the memory region, with an insulator layer exclusively in the logic region, using non-lead-based Perovskite materials and hardmask materials to enable precise control of device thickness and reduce electrical resistance, and encapsulation layers to protect the devices during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used on ferroelectric materials of varying thicknesses, then the etching process becomes difficult and imprecise, but attempting to etch all materials to uniform thickness would remove the ferroelectric material and destroy device functionality
Solution Approach 1:
The patent divides the etching process into two distinct stages: first etching the dielectric material to a first depth to form recesses, then etching the ferroelectric material within those recesses to a second depth. This segmentation allows each material type to be etched with appropriate parameters without affecting the other materials, resolving the contradiction between etching precision and manufacturing ease.
Solution Approach 2:
The patent applies different etching conditions and depths to different spatial locations and material types. The dielectric material is etched to a first depth in certain regions, while the ferroelectric material is etched to a second depth in other regions. This local differentiation enables precise control over each material's removal, achieving both high precision and manufacturing feasibility.
2Productivity
If the ferroelectric capacitor thickness is increased to achieve high-density arrays, then the device density improves, but the capacitor height exceeds the interconnect height constraints in adjacent logic regions
Solution Approach 1:
The patent embeds the ferroelectric capacitor within recesses formed in the dielectric material. By nesting the capacitor structure into the dielectric recesses rather than placing it on the surface, the overall height of the capacitor assembly is reduced while maintaining the active ferroelectric material thickness needed for high-density operation, thus satisfying interconnect height constraints.
Solution Approach 2:
The patent transitions from a planar surface-mounted capacitor structure to a vertically integrated structure where the capacitor is embedded within the dielectric layer. This dimensional reorganization allows the ferroelectric material to maintain its functional thickness while the overall structure fits within the height constraints of the interconnect architecture.
3Reliability
If lead-based ferroelectric materials are used to achieve desired electrical properties, then the electrical performance improves, but environmental harm and toxicity increase
Solution Approach 1:
The patent substitutes lead-based ferroelectric materials with non-lead-based alternative materials that exhibit comparable or improved electrical properties. By changing the material composition parameters while maintaining the necessary ferroelectric characteristics, the device achieves reliable electrical performance without the environmental and health hazards associated with lead toxicity.
Data Source
AI summary
A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.