Ferroelectric Capacitor Helmet Structure for Shorting Isolation
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Solution Overview
Problem
Current memory technologies, such as SRAM and DRAM, are volatile and not suitable for low power and compact computing due to high write energy, low density, and high power consumption, while non-volatile memories like MRAM and flash memories face challenges in scalability and integration for advanced technology nodes.
Innovation Solution
A method for forming a ferroelectric capacitor that involves depositing a stack of layers with conductive electrodes and ferroelectric material, using a non-conductive dielectric to prevent shorting, and a metal cap to protect the dielectric, allowing for the fabrication of ferroelectric capacitors in advanced technology nodes like 7 nm and below, enabling low voltage switching and higher density memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional memory structures (SRAM, DRAM) are used, then manufacturing is well-established, but power consumption is high and density is low
Solution Approach 1:
The patent combines logic circuitry and memory cells into a unified structure where transistors serve dual purposes as both logic elements and memory access devices. The memory cell shares transistors with the logic circuit, eliminating separate access transistors and reducing overall power consumption while maintaining manufacturability with existing CMOS processes
Solution Approach 2:
Transistors in the memory cell are designed to perform multiple functions: serving as access transistors for read/write operations, as logic elements for data processing, and as part of the memory storage structure. This multi-functionality reduces the total number of components needed, lowering power consumption and simplifying manufacturing
2Stability of the object's composition
If non-volatile memories (MRAM, flash) are used, then data retention is improved, but scalability to advanced technology nodes is limited
Solution Approach 1:
The patent employs ferroelectric materials with switchable polarization states that can be reliably formed and controlled at advanced technology nodes (7nm and below). By changing the material parameters and deposition conditions to accommodate smaller feature sizes, the invention achieves both non-volatile data retention and scalability to cutting-edge manufacturing processes
3Quantity of substance
If ferroelectric capacitor dimensions are reduced for higher density, then memory density is improved, but electrical shorting between electrodes becomes more likely
Solution Approach 1:
The patent introduces a vertically extending helmet structure that provides lateral separation between the top and bottom electrodes of adjacent ferroelectric capacitors. By moving from a planar separation approach to a three-dimensional structure with vertical walls, the invention achieves effective electrical isolation even when the capacitors are closely spaced, enabling higher memory density without compromising reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures non-volatile memory operation at lower voltages with higher density and prevents electrical shorting, enabling more efficient and scalable memory solutions for compact computing devices.
Implementation Method 1
enabling low voltage switching
Implementation Method 2
using a non-conductive dielectric to prevent shorting
Data Source
AI summary
Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.