Ferroelectric Capacitor Sidewall Protection Against Metal Shorting
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Solution Overview
Problem
The fabrication of ferroelectric random-access memory (FRAM) devices faces challenges due to the detrimental impact of ferroelectric capacitor materials and processes on metal-oxide-semiconductor (MOS) transistors and the increased potential for defects and errors in manufacturing, particularly in aligning interconnect layers, which can lead to electrical shorting.
Innovation Solution
The integration of protective etch stopping films along the sidewalls of ferroelectric capacitors, which etch slower than the dielectric layer, prevents electrical shorting by protecting the capacitors from misaligned metal interconnects during the fabrication process, allowing for tighter design rules and higher manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If protective etch stopping films are added along the sidewalls of ferroelectric capacitors, then manufacturing precision and reliability are improved by preventing electrical shorting from misaligned metal interconnects, but device complexity increases due to additional fabrication steps and materials
Solution Approach 1:
The etch stopping film is deposited on the sidewalls of the ferroelectric capacitor before the metal interconnect formation step. This preliminary protective layer is in place before the potential misalignment occurs during subsequent processing, allowing the metal interconnect to be deposited even if misaligned without causing electrical shorting to the ferroelectric capacitor.
Solution Approach 2:
The etch stopping film acts as an intermediary protective layer between the ferroelectric capacitor and the metal interconnect. This intermediate layer prevents direct contact between the metal interconnect and the ferroelectric capacitor when misalignment occurs, thereby preventing electrical shorting while allowing the metal interconnect to maintain its electrical connection to the electrode through the dielectric layer.
2Productivity
If tighter design rules are implemented to increase FRAM cell density, then productivity is improved by fitting more cells per chip, but manufacturing precision requirements become more stringent increasing the potential for defects
Solution Approach 1:
The etch stopping film provides a cushioning protective layer that compensates for potential misalignment errors. By having this protective layer in place beforehand, the design can tolerate tighter spacing between cells without increasing the risk of electrical shorting, thereby enabling higher cell density while maintaining manufacturing yield.
3Device complexity
If ferroelectric capacitor materials and processes are integrated with baseline CMOS process flow, then device complexity is reduced by using standard fabrication steps, but harmful factors increase as the ferroelectric materials detrimentally impact the MOS transistors
Solution Approach 1:
The fabrication process is segmented into distinct regions with different protective measures. The etch stopping film is selectively deposited only on the sidewalls of the ferroelectric capacitor, not on the entire wafer or on the MOS transistor regions. This localized approach protects the ferroelectric capacitor from misalignment damage while avoiding exposure of the MOS transistors to harmful ferroelectric processing conditions.
Data Source
AI summary
Disclosed herein is an apparatus that includes a ferrocapacitor having a sidewall. An etch stopping film is disposed along the sidewall of the ferrocapacitor, with a hydrogen barrier film disposed between the etch stopping film and the sidewall of the ferrocapacitor.