Ferroelectric Transistor Stack With Carbon Diffusion Barrier
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Silicon-based electronic devices face limitations in improving operating characteristics and scaling down due to subthreshold swing (SS) limitations, which restrict the reduction of operating voltage and increase power density.
Innovation Solution
Incorporating a carbon layer with an sp2 bonding structure, such as nanocrystalline graphene, between the substrate and ferroelectric layer in electronic devices, along with a gate electrode, to enhance subthreshold swing and prevent diffusion of metal or oxygen during high-temperature annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If silicon-based logic transistors are scaled down, then device size is reduced, but operating voltage cannot be lowered below 0.8V due to subthreshold swing limitation
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional silicon-based materials to low-dimensional carbon materials (graphene, nanotubes, or fullerenes). This material parameter change enables subthreshold swing to exceed 60 mV/dec, which fundamentally alters the voltage-scaling behavior and allows operating voltage to be reduced below the conventional 0.8V limit while maintaining transistor functionality.
2Length of moving object
If transistor size is reduced to improve scaling, then power density increases
Solution Approach 1:
By changing the gate electrode material to low-dimensional carbon materials, the patent achieves superior subthreshold swing characteristics that enable more aggressive voltage scaling. This parameter change in material composition allows for lower operating voltages that counterbalance the increased power density from miniaturization, thereby managing overall power consumption during scaling.
3Reliability
If high-temperature annealing is performed to crystallize ferroelectric layer, then ferroelectric properties are improved, but metal or oxygen diffusion into channel element occurs
Solution Approach 1:
The patent introduces a carbon layer as an intermediary barrier between the ferroelectric layer and the channel element. This intermediate carbon layer prevents direct diffusion pathways during high-temperature annealing, allowing the ferroelectric layer to be properly crystallized without contaminating the channel element with metal or oxygen diffusion.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including the carbon layer and ferroelectric layer. This composite material architecture combines the benefits of high-temperature processing for ferroelectric crystallization with the protective function of the carbon diffusion barrier, resolving the contradiction between achieving reliable ferroelectric properties and preventing harmful diffusion.
4Ease of manufacture
If conventional materials are used, then manufacturing process is simple, but subthreshold swing is limited to 60 mV/dec
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based gate electrodes to low-dimensional carbon materials. While this material substitution requires additional processing steps for deposition and crystallization, it fundamentally improves the subthreshold swing parameter from the conventional 60 mV/dec limit to values exceeding 60 mV/dec, achieving better device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration lowers the subthreshold swing below 60 mV/dec, reduces current leakage, and allows for easier scaling down of logic transistors by preventing undesired oxide layer formation, while maintaining uniformity and reducing total device thickness.
Implementation Method 1
the carbon layer may be configured to limit diffusion of at least one of metal or oxygen from the ferroelectric layer into the channel element
Implementation Method 2
crystallizing the ferroelectric layer through an annealing process
Implementation Method 3
The depositing of the carbon layer may be performed by chemical vapor deposition (CVD) or atomic layer deposition (ALD)
Implementation Method 4
The depositing of the carbon layer may be performed by chemical vapor deposition (CVD) or atomic layer deposition (ALD)
Data Source
AI summary
Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.