Ferroelectric Memory Chiplet Layout for High-Bandwidth AI Packaging
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Solution Overview
Problem
Existing AI processing systems face limitations in I/O bandwidth and thermal management due to the stacking of dynamic random-access memory (DRAM) on top of a compute die, leading to increased latency and power consumption.
Innovation Solution
The proposed solution involves an integrated circuit package design where the memory die is positioned below the compute die, allowing for direct face-to-face alignment of active devices and reducing the need for high-density through-silicon vias, while also enabling tighter micro-bump spacing for improved bandwidth and efficient thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is stacked on top of compute die, then memory capacity is increased, but I/O bandwidth is limited and thermal management becomes difficult
Solution Approach 1:
The patent inverts the conventional stacking order by placing the memory die below the compute die instead of above it. This inversion allows the active devices of both dies to be face-to-face aligned, enabling direct coupling without requiring high-density through-silicon vias in the compute die, thereby maintaining high I/O bandwidth while providing memory capacity.
Solution Approach 2:
The patent transitions from a vertical stacking approach (which limits I/O bandwidth) to a face-to-face horizontal alignment approach. By aligning the active devices of the compute die and memory die face-to-face, the patent creates direct coupling paths that significantly increase I/O bandwidth and enable ultra-high bandwidth memory access.
2Quantity of substance
If DRAM is stacked on top of compute die, then memory capacity is increased, but thermal management becomes difficult
Solution Approach 1:
By inverting the stacking order and placing memory die below the compute die, the patent enables the compute die to be positioned adjacent to the heat sink rather than having the heat sink blocked by the memory die. This inversion resolves the thermal management issue while maintaining memory capacity.
3Productivity
If face-to-face alignment of active devices is implemented, then I/O bandwidth is increased, but manufacturing complexity increases
Solution Approach 1:
The patent simplifies manufacturing by inverting the stacking order. Instead of requiring high-density through-silicon vias to penetrate the compute die (which is complex and time-consuming), the inverted approach allows direct face-to-face coupling of active devices between compute die and memory die, eliminating the need for dense TSV fabrication while maintaining high I/O bandwidth.
4Productivity
If micro-bump spacing is reduced, then bandwidth is increased, but manufacturing precision requirements increase
Solution Approach 1:
By inverting the stacking order and implementing face-to-face alignment of active devices, the patent enables tighter micro-bump spacing to be achieved more easily. The direct coupling configuration allows micro-bumps to be positioned closer together without requiring extremely high manufacturing precision, as the alignment is established during the bonding process rather than requiring pre-formed high-density TSV patterns.
Data Source
AI summary
A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.