Ferroelectric Logic Chiplet Stacking for Bandwidth and Thermal Paths
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Solution Overview
Problem
Current AI processor systems face challenges in reducing latency and power consumption, and managing thermal issues due to hardware-intensive computing, particularly in multi-dimensional packaging setups where the compute die is stacked below the memory die, leading to thermal management difficulties and limited I/O bandwidth.
Innovation Solution
The proposed solution involves a logic-on-logic stacking configuration where the compute die is positioned on top of a memory die, with ferroelectric or paraelectric logic used in the compute chiplets, allowing for ultra-high bandwidth and efficient thermal management by placing the heat-generating compute die closer to the heat sink and reducing the perforation requirements of the memory die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the compute die is stacked below the memory die in traditional multi-dimensional packaging, then the I/O bandwidth is limited and thermal management becomes difficult, but the memory die can be efficiently connected to the package substrate
Solution Approach 1:
The patent inverts the traditional stacking order by placing the compute die on top of the memory die instead of below it. This inversion allows the compute die to be directly connected to the package substrate, enabling efficient thermal management through direct thermal paths while also improving I/O bandwidth by eliminating the need for signals to pass through the memory die.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration, but with a different stacking order. By utilizing the vertical dimension and placing the compute die on top, the patent achieves improved thermal management and I/O bandwidth while maintaining high-density integration.
2Temperature
If the compute die is positioned on top of the memory die, then thermal management is improved and I/O bandwidth is increased, but the perforation requirements of the memory die are reduced which may affect structural integrity
Solution Approach 1:
The patent segments the package into distinct functional layers with the memory die forming a complete, non-perforated substrate layer. This segmentation allows the memory die to maintain its structural integrity while the compute die above it is perforated to accommodate thermal management features and I/O connections.
Solution Approach 2:
The patent introduces an intermediary thermal management layer between the compute die and the package substrate. This intermediary structure provides thermal pathways without requiring perforations through the memory die, thus maintaining the memory die's structural integrity while achieving efficient thermal management.
3Device complexity
If traditional stacking configurations are used, then the package structure is simple, but thermal issues are exacerbated and latency is increased
Solution Approach 1:
By inverting the stacking order with the compute die on top, the patent reduces the distance data must travel between the compute die and the package substrate, thereby reducing latency. The inverted configuration also simplifies the overall package structure by eliminating complex interconnect paths through the memory die.
Data Source
AI summary
A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.