Ferroelectric Complementary FET for Low-Power Logic
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Solution Overview
Problem
The IT industry faces increasing power dissipation as logic functions are integrated at higher densities on computer chips, with conventional CMOS devices limited by a 60 mV/decade requirement on voltage swing, making it challenging to reduce power-supply voltage effectively.
Innovation Solution
A field-effect transistor (FET) design incorporating a common ferroelectric gate and channel area with both n and p channels, utilizing a ferroelectric gate stack that includes a gate insulating layer and a ferroelectric material layer, which increases capacitance and voltage gain, allowing the device to operate at lower voltages and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CMOS devices are used with higher integration density, then logic function integration increases, but power dissipation increases
Solution Approach 1:
The patent changes the fundamental operating parameters of the FET by introducing a ferroelectric gate material that enables negative capacitance operation. This allows the device to achieve steeper subthreshold slopes and higher transconductance at lower supply voltages, thereby maintaining high integration density while reducing power dissipation through lower operating voltages and improved switching efficiency.
Solution Approach 2:
The patent employs a composite gate structure consisting of a ferroelectric material layer combined with metal gate electrodes and insulating layers. This composite material approach creates a negative capacitance effect that amplifies the gate voltage, enabling enhanced device performance and lower power operation while maintaining high integration density.
2Loss of energy
If power-supply voltage is reduced to lower power dissipation, then energy consumption decreases, but voltage swing requirement limits further reduction
Solution Approach 1:
The ferroelectric gate material fundamentally changes the voltage-parameter relationship by providing negative capacitance that amplifies small input voltage swings. This enables the device to achieve full logic swing and proper operation at supply voltages below conventional thresholds, breaking the 60 mV/decade limitation and allowing continued voltage scaling for reduced power consumption.
3Power
If ferroelectric gate stack with both n and p channels is integrated, then capacitance and voltage gain increase, but device structure complexity increases
Solution Approach 1:
The patent merges the n-channel and p-channel FET structures into a single integrated device sharing a common ferroelectric gate stack. This consolidation achieves the benefits of complementary operation with high voltage gain and capacitance while reducing the overall device count and interconnect complexity compared to separate nFET and pFET implementations.
Solution Approach 2:
The ferroelectric gate stack serves multiple functions simultaneously: it provides the gate control for both n and p channels, generates negative capacitance for voltage amplification, and enables low-voltage operation. This multi-functionality reduces the need for additional dedicated components, offsetting the inherent structural complexity with functional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FET design achieves voltage amplification and reduced power consumption by utilizing a ferroelectric gate stack, enabling operation at lower voltages than conventional CMOS devices, thereby addressing the challenge of increasing power dissipation in high-density chip integration.
Implementation Method 1
a ferroelectric material layer disposed on the gate insulating layer
Data Source
AI summary
A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.