Non-volatile Content Addressable Memory Using Ferroelectric Transistors
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Solution Overview
Problem
Conventional content addressable memory devices have large unit cell sizes due to their volatile nature and complex configurations, which hinder integration and efficiency.
Innovation Solution
The use of a non-volatile content addressable memory device configuration featuring two ferroelectric transistors of different types, connected in series or parallel, with shared word, match, and search lines, and a 2T-0R-0C cell structure, allowing for reduced cell size and increased integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM-based TCAM is used, then data retention is achieved, but unit cell area becomes large
Solution Approach 1:
The patent changes the fundamental parameter of memory material from volatile SRAM to non-volatile ferroelectric material, enabling data retention without requiring the complex 16-transistor SRAM cell structure. This parameter change allows achieving both data retention and reduced cell area simultaneously.
Solution Approach 2:
The patent extracts and removes the volatile memory component (SRAM) from the TCAM structure, replacing it with non-volatile ferroelectric transistors. This extraction eliminates the need for complex volatile memory circuits while maintaining data retention capability through the intrinsic non-volatile nature of ferroelectric material.
2Reliability
If SRAM-based TCAM structure is used, then data storage is achieved, but device complexity increases
Solution Approach 1:
The patent changes the storage mechanism parameter from volatile electrical state in SRAM to non-volatile polarization state in ferroelectric material. This enables data storage with significantly fewer transistors per cell, reducing device complexity while maintaining storage functionality.
Solution Approach 2:
The patent removes the complex SRAM cell structure (16 transistors) and replaces it with a simplified ferroelectric transistor-based cell. This extraction of the volatile memory component eliminates the need for complex cross-coupled transistor networks while preserving data storage capability through non-volatile polarization states.
3Productivity
If non-volatile memory structure is implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent changes the material parameter to ferroelectric, which can be integrated using standard semiconductor fabrication processes. This parameter change enables high integration density while maintaining compatibility with existing manufacturing techniques, avoiding the need for entirely new fabrication methodologies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the unit cell size, enhances integration, and simplifies operations by applying the same voltage to NMOS and PMOS ferroelectric transistors during writing and reading, thereby improving the memory device's performance and manufacturing efficiency.
Implementation Method 1
a ferroelectric layer arranged on the substrate between the first and second doped layers
Data Source
AI summary
Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.