Ferroelectric Gate Stack Defect Extraction for Device Tuning
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Solution Overview
Problem
Accurately determining the influence of ferroelectric and paraelectric layers on the performance of semiconductor devices is challenging due to the difficulty in quantitatively monitoring and controlling defects in the gate insulating layer and its interface.
Innovation Solution
A ferroelectric electronic device with a specific structure including a first layer, an insulating layer with a ferroelectric layer and a paraelectric layer, and an upper electrode, where defect densities are extracted using low-frequency noise analysis and current-voltage measurement methods to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If only the number of defects in an entire gate insulating layer including a ferroelectric layer is considered, then the measurement is simple, but accurately determining the influence of the ferroelectric layer and/or paraelectric layer on device performance becomes difficult
Solution Approach 1:
The patent segments the gate insulating layer into distinct regions (paraelectric layer and ferroelectric layer) and applies different measurement methods to each region. Low-frequency noise analysis is used to extract bulk defect density from the paraelectric layer, while current-voltage measurements are used to extract interface defect density at the semiconductor-insulating layer interface. This segmentation allows accurate determination of defect densities in specific layers rather than treating the entire gate insulating layer as a single unit.
2Ease of manufacture
If defect density is not quantitatively monitored and controlled, then the device fabrication process is simpler, but the performance of ferroelectric semiconductor devices cannot be optimized
Solution Approach 1:
The patent implements a feedback mechanism where defect densities are extracted from measured electrical characteristics (low-frequency noise and current-voltage data) and used to control the fabrication process. The extracted bulk defect density and interface defect density values provide quantitative feedback that allows optimization of fabrication parameters such as deposition conditions, annealing temperature, and layer thickness to achieve desired device performance while maintaining manufacturing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables quantitative monitoring and control of defect densities, improving the performance of ferroelectric semiconductor devices by adjusting process parameters based on extracted defect densities, thereby enhancing device characteristics such as negative capacitance and threshold voltages.
Implementation Method 1
A defect in a gate insulating layer and an interface of the gate insulating layer acts as an important parameter for implementing negative capacitance of a ferroelectric-based logic semiconductor device
Implementation Method 2
extracting a first defect density per volume in the insulating layer of the ferroelectric electronic device by low-frequency noise analysis
Implementation Method 3
extracting a second defect density per area in a region of the first interface by a current-voltage measurement method
Data Source
AI summary
Provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. A ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 1016 cm−3eV−1 or more and an interface defect density of 1010 cm−2eV−1 or more.