Ferroelectric Gate Stack Defect Extraction for Threshold Control
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Solution Overview
Problem
Accurately determining the influence of ferroelectric and paraelectric layers on the performance of semiconductor devices is challenging due to the difficulty in quantitatively monitoring and controlling defects in the gate insulating layer and its interface.
Innovation Solution
A ferroelectric electronic device with a specific structure including a first layer, an insulating layer with a ferroelectric layer and a paraelectric layer, and an upper electrode, where defect densities are extracted using low-frequency noise analysis and current-voltage measurement methods to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If defect density in the entire gate insulating layer is measured, then the measurement covers all defects including ferroelectric and paraelectric layers, but it becomes difficult to accurately determine the individual influence of ferroelectric and paraelectric layers on device performance
Solution Approach 1:
The patent applies segmentation by dividing the gate insulating layer into distinct regions: the first insulating layer (paraelectric layer) and the second insulating layer (ferroelectric layer). By forming these layers with different dielectric constants and measuring capacitance at different voltage ranges, the patent enables separate characterization of each layer's defect density, resolving the contradiction between comprehensive measurement and accurate individual layer analysis.
Solution Approach 2:
The patent implements local quality by assigning different material properties to different layers: the first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant. This allows targeted measurement approaches where specific voltage ranges and measurement conditions can be applied to extract defect density information from individual layers rather than treating the entire stack uniformly.
2Reliability
If the gate insulating layer is designed with multiple layers to achieve desired electrical characteristics, then device performance is improved, but the difficulty of quantitatively monitoring and controlling defects increases
Solution Approach 1:
The patent employs feedback mechanisms by establishing relationships between measurement parameters (capacitance, conductance) and defect density, and between defect density and device performance characteristics (threshold voltage, subthreshold swing). This enables process control where measurement results feed back into defect management strategies, allowing quantitative monitoring of defects in multi-layer structures and facilitating optimization of layer formation processes.
3Manufacturing precision
If process parameters are adjusted to control defect density, then device performance is enhanced, but the complexity of process optimization increases
Solution Approach 1:
The patent applies parameter changes by identifying and controlling key process parameters such as deposition temperature, deposition rate, and layer thickness during the formation of the gate insulating layer. By establishing relationships between these parameters and the resulting defect density in each layer, the patent enables systematic optimization of manufacturing processes to achieve desired defect levels while managing process complexity through focused parameter control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables quantitative monitoring and control of defect densities, improving the performance of ferroelectric semiconductor devices by adjusting process parameters based on extracted defect data, thereby enhancing device characteristics such as negative capacitance and threshold voltages.
Implementation Method 1
A defect in a gate insulating layer and an interface of the gate insulating layer acts as an important parameter for implementing negative capacitance of a ferroelectric-based logic semiconductor device
Implementation Method 2
securing a hysteresis curve of a memory semiconductor device
Data Source
AI summary
Provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. A ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 1016 cm−3 eV−1 or more and an interface defect density of 1010 cm−2 eV−1 or more.