Ferroelectric Dielectric Layer Doping for Reliable High-Density Memory
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Solution Overview
Problem
Existing HfO2-doped ferroelectric thin films in flash memory devices face reliability issues such as operating voltage approaching breakdown voltage and fatigue, limiting their development in accordance with Moore's Law.
Innovation Solution
A semiconductor device is developed using a dielectric material layer containing a metal interstitial impurity, where the material is a compound with a chemical formula XaY1−aZbW, and the dielectric material layer is configured to undergo crystallization by subjecting it to electricity, heat, light, or magnetism, transitioning from an amorphous to a crystalline state with ferroelectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If HfO2-doped ferroelectric thin film is used to increase memory capacity, then dielectric constant is improved, but reliability deteriorates due to operating voltage approaching breakdown voltage and fatigue
Solution Approach 1:
The patent changes the chemical composition parameters of the dielectric material by introducing metal interstitial impurities (such as hafnium, zirconium, or rare earth elements) at controlled concentrations (0.05≤b≤0.5 in the formula XaY1−aZbW). This compositional modification allows the material to achieve ferroelectric properties with lower coercive electric field while maintaining higher breakdown voltage, thus resolving the contradiction between memory capacity and reliability
Solution Approach 2:
The patent creates a composite dielectric material system by combining base dielectric material (XaY1−aW) with metal interstitial impurity (Zb). This composite structure leverages the synergistic effects of different elements to achieve both high dielectric constant for memory capacity and enhanced reliability through improved electrical breakdown characteristics and reduced fatigue
2Quantity of substance
If device size is reduced to increase memory capacity, then memory capacity is improved, but manufacturing cost increases
Solution Approach 1:
The patent modifies the material composition parameters to achieve ferroelectric properties in a more cost-effective manner. By using metal interstitial impurities that can be integrated into existing semiconductor manufacturing processes, the solution avoids the need for entirely new fabrication techniques, thereby reducing manufacturing costs while enabling higher density memory devices
3Quantity of substance
If device size is reduced to increase memory capacity, then memory capacity is improved, but reliability deteriorates due to size reduction effects
Solution Approach 1:
The patent changes the material composition by incorporating metal interstitial impurities that stabilize the ferroelectric phase at smaller dimensions. The specific compositional parameters (0.05≤b≤0.5) are optimized to maintain reliable ferroelectric switching behavior even in miniaturized devices, counteracting the reliability degradation typically associated with size reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of metal interstitial impurities in the dielectric material layer enhances ferroelectric properties, reduces the coercive electric field, and improves reliability, making the semiconductor device suitable for high-density, low-power non-volatile memory applications.
Implementation Method 1
the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state
Implementation Method 2
the metal interstitial impurity in the lattice interstice of the dielectric material layer in the crystalline state causes lattice expansion and lattice deformation, so as to generate a tensile stress and/or a compressive stress
Data Source
AI summary
The present disclosure provides a semiconductor device based on a dielectric material containing a metal interstitial impurity, including: a substrate, a dielectric material layer, and a functional layer. A material for preparing the dielectric material layer is a compound containing the metal interstitial impurity. The dielectric material layer and/or the functional layer is configured to subject to at least one of electricity, heat, light or magnetism, such that the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state.