Ferroelectric Gate Dielectric Testing for Sub-60 mV MOS Switching
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Solution Overview
Problem
Current MOS devices are limited by a sub-threshold swing of 60 mV/decade, making it difficult to switch faster due to the drift-diffusion transport mechanism, which restricts further scaling of operation voltage and threshold voltage, and this limitation applies to FinFET and ultra-thin-body MOSFET on silicon-on-insulator devices as well.
Innovation Solution
The formation of a ferroelectric dielectric layer with a specific crystalline structure and thickness is achieved through in-line monitoring during manufacturing, using techniques like piezoresponse force microscopy, X-ray diffraction, and ellipsometry to ensure the layer provides negative capacitance, reducing the sub-threshold swing and enhancing switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional MOS devices use drift-diffusion transport mechanism, then device structure is simple and manufacturing is easy, but sub-threshold swing is limited to 60 mV/decade which restricts switching speed
Solution Approach 1:
The patent employs a composite material structure consisting of a ferroelectric dielectric layer (e.g., HfO2) combined with a metal gate electrode. This composite structure enables negative capacitance effect that reduces sub-threshold swing below the conventional 60 mV/decade limit, thereby improving switching speed while maintaining manufacturability through established semiconductor fabrication processes.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate dielectric by introducing a ferroelectric material with specific crystalline phases (orthorhombic or tetragonal). By controlling the dielectric constant and introducing negative capacitance characteristics, the device achieves enhanced switching performance with sub-60 mV/decade sub-threshold swing without fundamentally altering the basic MOS device architecture.
2Speed
If ferroelectric dielectric layer is added to reduce sub-threshold swing, then switching speed increases, but manufacturing process complexity increases
Solution Approach 1:
The patent incorporates the ferroelectric dielectric layer formation as an early step in the gate stack fabrication process, before subsequent metal gate electrode deposition. By preparing the ferroelectric layer in advance with proper thickness control and crystalline structure, the manufacturing process integrates smoothly with existing CMOS fabrication flows, minimizing additional process complexity while achieving the desired electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a ferroelectric dielectric layer with a controlled orthorhombic crystalline structure allows for lower sub-threshold swing, thereby increasing the switching speed of semiconductor devices and enabling faster operation compared to devices without such layers.
Implementation Method 1
The use of a ferroelectric dielectric layer with a controlled orthorhombic crystalline structure allows for lower sub-threshold swing, thereby increasing the switching speed of semiconductor devices
Implementation Method 2
using techniques like piezoresponse force microscopy, X-ray diffraction, and ellipsometry to ensure the layer provides negative capacitance
Implementation Method 3
using techniques like piezoresponse force microscopy, X-ray diffraction, and ellipsometry to ensure the layer provides negative capacitance
Data Source
AI summary
A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.