Dual Sample Read Method for Ferroelectric Memory Noise Reduction
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Solution Overview
Problem
Passive matrix-addressable ferroelectric or electret memory arrays face challenges in improving signal-to-noise ratio due to sampling noise and voltage noise, particularly as the size of memory arrays increases, leading to increased bit error rates and noise from parasitic couplings and sensing circuitry.
Innovation Solution
The implementation of a dual sample method, which involves taking two samples during the read operation – one before and one after applying a read voltage with switching capability – to deduct offset noise, combined with the use of a secondary amplifier stage with lower gain and bandwidth to mitigate thermal noise, thereby improving the signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory array size is increased to improve storage capacity, then productivity is improved, but measurement precision deteriorates due to increased sampling noise and voltage noise from parasitic couplings
Solution Approach 1:
The sensing operation is segmented into two separate sampling phases: first sampling before applying read voltage to capture offset noise, and second sampling after applying read voltage to capture signal plus noise. This segmentation allows the offset noise to be subtracted from the second sample, improving the signal-to-noise ratio while maintaining high storage capacity
Solution Approach 2:
The method changes the operational parameters by performing two samples at different voltage states (0V and read voltage) and subtracting the results. This parameter change approach eliminates offset noise while preserving the signal, enabling accurate reading even in large memory arrays where parasitic couplings would otherwise degrade performance
2Measurement precision
If sensing amplification is increased to improve signal detection, then measurement precision is improved, but object-generated harmful factors worsen due to increased thermal noise from the sensing circuitry
Solution Approach 1:
The first sampling is performed before applying the read voltage to capture the offset noise and thermal noise baseline. This preliminary action establishes a reference that can be subtracted from the second sample, reducing the impact of thermal noise generated by the sensing circuitry while maintaining signal detection capability
Solution Approach 2:
The thermal noise and offset noise generated by the sensing circuitry are converted from harmful factors into useful information. By sampling before and after the read voltage application and subtracting the results, the noise components are eliminated while the signal is preserved, effectively converting noise into a benefit for accurate signal detection
3Ease of manufacture
If passive matrix architecture is used to simplify manufacturing and increase integration density, then ease of manufacture is improved, but object-generated harmful factors worsen due to sneak currents affecting multiple cells sharing common electrodes
Solution Approach 1:
The reading operation uses periodic voltage pulses applied to word lines and bit lines in a coordinated sequence. By applying voltages periodically and systematically to adjacent cells, the method ensures that sneak currents flow symmetrically and cancel out, eliminating their harmful effect while maintaining the manufacturing simplicity of passive matrix architecture
Data Source
AI summary
In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means connected to the bit line of memory cell is activated in order to initiate a charge measurement and a first charge value is registered, whereafter a switching voltage is applied to the memory cell and a second charge value is registered. A readout value is obtained by subtracting the first charge value from the second charge value. A sensing device for performing an embodiment of the method comprises a first amplifier stage with an integrator circuit and connected with a second amplifier stage (A2) following the first amplifier stage and with an integrator circuit, and a sampling capacitor connected between an output of the first amplifier stage and an input of the second amplifier stage.