2T-1C Ferroelectric eDRAM Cell for Small-Capacitor Readout
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Solution Overview
Problem
Conventional eDRAM architectures face limitations in scaling due to the need for larger ferroelectric capacitors to achieve sufficient signal levels, leading to increased memory cell size and lower density, especially as dimensions shrink below the 10 nanometer node.
Innovation Solution
The implementation of a two transistor one capacitor (2T-1C) architecture with trench and/or planar ferroelectric capacitors, where a second transistor acts as a sense transistor to enable readout of smaller capacitor charges, allowing for independent read and write paths and non-destructive read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional eDRAM architectures use larger ferroelectric capacitors to achieve sufficient signal levels, then signal quality is improved, but memory cell size increases and density decreases
Solution Approach 1:
The patent divides the read operation into two separate transistors: an access transistor for writing data and a sense transistor for reading data. This segmentation allows the ferroelectric capacitor to be smaller while still achieving sufficient signal levels, because the sense transistor is specifically optimized for high-gain readout operations. The separation of write and read functions enables independent optimization of each transistor's characteristics.
Solution Approach 2:
The sense transistor acts as an intermediary between the small ferroelectric capacitor and the readout circuitry. It provides signal amplification and conversion, enabling small capacitor charges to be converted into readable signals with sufficient margin. This intermediary device allows the system to use smaller capacitors while maintaining reliable readout signals.
2Area of stationary object
If feature size is scaled down to increase device density, then memory density is improved, but fabrication process variability increases and manufacturing becomes more difficult
Solution Approach 1:
The patent changes the architectural parameters of the memory cell by introducing a 2T-1C configuration instead of the conventional 1T-1C. This parameter change allows the use of smaller capacitors with reduced signal levels, which can be manufactured with better precision at scaled dimensions. The sense transistor compensates for the smaller capacitor size, maintaining signal integrity while enabling smaller feature sizes and higher density.
3Device complexity
If a single transistor architecture is used, then device complexity is reduced, but the ability to perform non-destructive read operations is lost
Solution Approach 1:
By segmenting the transistor functions into access and sense roles, the patent enables non-destructive read operations while maintaining reasonable complexity. The sense transistor is configured to read the capacitor state without completely discharging it, allowing the data to be preserved after reading. This functional segmentation provides the versatility needed for advanced read operations.
Solution Approach 2:
The access transistor serves multiple functions: it controls writing data to the capacitor and also participates in the read operation by controlling access to the capacitor. This multi-functionality helps offset the increased complexity from adding a second transistor, as the access transistor is already present for write operations and is now reused for read operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the use of smaller ferroelectric capacitors, improving memory density and performance by converting capacitor charge into readable signals, while maintaining independent control over read/write operations.
Implementation Method 1
trench and/or planar ferroelectric capacitors
Implementation Method 2
converting capacitor charge into readable signals
Data Source
AI summary
Embodiments disclosed herein include a memory device. In an embodiment, the memory device comprises a first transistor, where the first transistor is an access transistor to write data. In an embodiment, the memory device further comprises a ferroelectric capacitor for storing data. In an embodiment, the memory device further comprises a second transistor, where the second transistor is a sense transistor to read the data stored on the ferroelectric capacitor.