Ferroelectric FET Pbits for Low-Power AI Random Number Generation
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Solution Overview
Problem
Traditional CMOS devices for artificial intelligence (AI) applications face challenges in power, performance, and area efficiency, and magnetic pbits are prone to magnetic attacks and stray fields, introducing noise and additional footprint.
Innovation Solution
Employing ferroelectric field-effect transistor (FEFET) designs that utilize the intrinsic probabilistic nature of ferroelectric polarization switching for generating binary random numbers, offering higher output ratios, robustness against magnetic attacks, and faster operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional CMOS devices are used for AI applications, then device compatibility and maturity are maintained, but power efficiency, performance, and area utilization deteriorate
Solution Approach 1:
The patent changes the fundamental operating parameter from deterministic voltage switching in CMOS to probabilistic polarization switching in ferroelectric materials. By utilizing the stochastic nature of ferroelectric polarization reversal, the device achieves probabilistic computing functionality with superior power efficiency while maintaining compatibility with standard semiconductor fabrication processes
Solution Approach 2:
The invention employs a composite structure combining ferroelectric material layer with standard CMOS transistor architecture. This hybrid approach integrates the probabilistic switching特性 of ferroelectric materials with the成熟工艺 of CMOS technology, achieving both power efficiency improvements and manufacturing compatibility
2Reliability
If magnetic pbits are used for probabilistic computing, then random number generation capability is achieved, but susceptibility to magnetic attacks and stray fields increases, introducing noise and additional footprint
Solution Approach 1:
The patent substitutes magnetic field-based switching with electric field-based polarization switching in ferroelectric materials. This replacement eliminates susceptibility to magnetic attacks and stray fields while maintaining the probabilistic switching functionality, thereby improving reliability without introducing magnetic noise
Solution Approach 2:
The ferroelectric polarization state serves as an intermediary that stores probabilistic information without requiring magnetic fields. This intermediary mechanism isolates the computing function from magnetic interference, providing inherent protection against magnetic attacks and reducing noise
3Productivity
If ferroelectric FET designs are employed for probabilistic computing, then power efficiency and speed are improved, but device fabrication complexity increases
Solution Approach 1:
The ferroelectric FET structure is designed to serve multiple functions: probabilistic switching, non-volatile memory storage, and logic computation. This multi-functionality reduces the need for separate components, simplifying the overall system fabrication while maintaining high computing speed and power efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
FEFET-based pbits provide improved power, performance, and area efficiency, with enhanced robustness and speed, enabling efficient computation for AI applications like optimization and sampling.
Implementation Method 1
a first field-effect transistor (FET) comprising: a source region; a drain region; a source electrode on the source region; a drain electrode on the drain region; a channel region between the source and drain regions; a dielectric layer on a surface over the channel region; an electrode layer above the dielectric layer; and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer
Data Source
AI summary
A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.


