Ferroelectric Fin Transistor Layout for Stronger Memory Cell Fields
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits leads to challenges in maintaining efficient transistor performance due to increased complexity and reduced geometry, particularly in the integration of memory cells where the thickness of the channel layer affects the electric field strength, compromising efficiency and performance.
Innovation Solution
The integration of a ferroelectric layer with a hydrogen blocking layer and a channel layer configuration where the channel layer is disposed aside the source and drain patterns, reducing the distance between the electrodes and storage layer to enhance the electric field strength and improve memory cell efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel layer thickness is reduced to scale down the transistor geometry, then the transistor size decreases and production efficiency increases, but the electric field strength decreases and transistor performance deteriorates
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional FinFET structure with vertical fins. This dimensional change allows the channel to extend vertically, increasing the effective channel area and electric field strength without increasing the lateral footprint, thus maintaining transistor performance while achieving scaling down.
Solution Approach 2:
The patent employs a composite structure combining the channel layer with surrounding dielectric materials and metal gates. This composite approach enables better electric field confinement and control, maintaining strong electric fields in the scaled-down device through the synergistic interaction of different materials with complementary properties.
2Ease of manufacture
If the distance between electrodes and storage layer is increased to accommodate standard memory cell structure, then the manufacturing process is simplified, but the electric field strength decreases and memory cell efficiency deteriorates
Solution Approach 1:
The patent utilizes vertical stacking to position the channel layer adjacent to the storage layer in the vertical dimension rather than requiring large lateral separation. This three-dimensional arrangement reduces the distance between electrodes and storage layer, enhancing electric field strength and memory cell efficiency while maintaining manufacturability.
3Device complexity
If standard transistor structure is used without hydrogen blocking layer, then the manufacturing process is simpler, but hydrogen diffusion occurs causing threshold voltage instability
Solution Approach 1:
The patent introduces a hydrogen blocking layer as an intermediary between the channel layer and the environment. This intermediate layer acts as a diffusion barrier, preventing hydrogen from reaching and degrading the channel layer, thus stabilizing threshold voltage while adding minimal structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency and performance of memory cells by maintaining a strong electric field and preventing hydrogen diffusion, thereby stabilizing the threshold voltage and improving overall transistor performance.
Implementation Method 1
a ferroelectric layer and a source/drain material layer are formed on the gate electrode. A first dielectric layer, an etch stop layer, and a second dielectric layer are sequentially formed on the source/drain material layer
Implementation Method 2
The channel layer has a base and fins protruding from the base. The base is in contact with the ferroelectric layer, and the fins are located between the source pattern and the drain pattern
Data Source
AI summary
A transistor includes a gate electrode, a ferroelectric layer, a source pattern, a drain pattern, and a channel layer. The ferroelectric layer is disposed on the gate electrode. The source pattern and the drain pattern are disposed over the ferroelectric layer. The channel layer has a base and fins protruding from the base. The base is in contact with the ferroelectric layer. The fins are located between the source pattern and the drain pattern.