Ferroelectric Fusion Memory for SoC Integration and Low-Power Synapses
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Solution Overview
Problem
Conventional DRAM and NAND memory technologies cannot be integrated into a single System on Chip (SoC), limiting storage capacity and computing capability, and synaptic devices in neural networks face issues with high operating current and power consumption.
Innovation Solution
The development of fusion memory cells that include a bulk substrate, source and drain, a channel region, and a ferroelectric layer with a gate, allowing operation in both charge trap and polarization reversal modes, combining the advantages of DRAM and NAND, and utilizing a ferroelectric layer with materials like HfOx, ZrOx, PZT, or BST, and doping elements for efficient data storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DRAM and NAND are manufactured using different processes, then each memory type can be optimized for its specific function, but they cannot be integrated into the same SoC, limiting storage capacity and computing capability
Solution Approach 1:
The patent merges DRAM and NAND manufacturing processes into a unified process flow. The fusion memory cell structure integrates DRAM-like transistor configuration with NAND-like floating gate architecture, allowing both memory types to be fabricated using the same process steps on the same substrate, enabling SoC integration while maintaining functional optimization for each memory type
Solution Approach 2:
The patent creates a universal manufacturing process that can produce both volatile and non-volatile memory functions. The fusion memory cell can operate in different modes (volatile DRAM mode and non-volatile NAND mode) depending on programming, providing multi-functionality from a single structure and process, thereby enabling diverse storage solutions within the same SoC
2Productivity
If conventional synaptic devices use parallel NOR structure with current convergence, then neural network calculations can be performed, but operating current and training power consumption become excessively large, limiting the number of parallels
Solution Approach 1:
The patent replaces the conventional current-convergence-based computing mechanism with a voltage-based mechanism utilizing ferroelectric polarization. Instead of summing currents from multiple parallel paths (which requires large current handling capability), the invention uses voltage signals that exploit the high breakdown voltage and low leakage characteristics of ferroelectric materials, enabling high-parallel computing with minimal power consumption
Solution Approach 2:
The patent changes the fundamental operating parameter from current to voltage. By using voltage-controlled ferroelectric polarization states instead of current convergence, the system achieves the same computational function with dramatically reduced power consumption. The high breakdown voltage of ferroelectric materials allows for high-parallel operation without the current handling limitations of conventional approaches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Fusion memory enables faster programming and erasing speeds with lower voltages than conventional DRAM and NAND, while maintaining better retention characteristics, and reduces power consumption in neural networks by optimizing synaptic device operations.
Implementation Method 1
a ferroelectric layer on the channel... an absolute value of the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed
Data Source
AI summary
The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.