Ferroelectric Semiconductor Stack for 3D GAA Memory Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating three-dimensional gate-all-around (GAA) transistors with nano-sheet or nano-wire channel regions, particularly in achieving efficient integration of transistor and memory structures with high device density and performance while managing etch selectivity and material compatibility.
Innovation Solution
A method is developed for fabricating semiconductor structures using nano-structure transistors and memory structures, involving the formation of channel and sacrificial semiconductor layers, etch stop layers, and gate dielectric materials, with a wafer bonding process to stack transistors over memory structures, enabling precise control of layer thickness and material composition for improved etch selectivity and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional gate-all-around transistor structures are implemented to increase device density, then device density and performance are improved, but fabrication complexity and etch selectivity challenges increase
Solution Approach 1:
The semiconductor structure is divided into multiple alternating layers of first semiconductor material and second semiconductor material, creating distinct sacrificial regions and channel regions. This segmentation enables selective etching processes to form the gate-all-around structure without requiring complex single-step fabrication, thereby increasing device density while managing fabrication complexity.
Solution Approach 2:
Sacrificial regions of the second semiconductor material are formed in advance within the stacked layers before the final gate structure is created. These preliminary sacrificial structures guide subsequent etching processes, simplifying the overall fabrication by pre-defining where material removal should occur to achieve the desired gate-all-around configuration.
2Manufacturing precision
If multiple alternating semiconductor layers are formed to enable gate-all-around structure, then etch selectivity is improved, but manufacturing process complexity increases
Solution Approach 1:
Different regions of the semiconductor structure have different material compositions - alternating layers of first semiconductor material and second semiconductor material with distinct etch characteristics. This local variation in material quality enables selective etching of sacrificial regions while preserving channel regions, improving etch selectivity despite the increased manufacturing process complexity.
Solution Approach 2:
The semiconductor structure uses composite alternating layers of different semiconductor materials (e.g., Si/SiGe, Si/SiC) with different etch rates and properties. This composite material approach enables precise control over etching behavior, allowing selective removal of sacrificial regions to form gate-all-around structures while managing the complexity of manufacturing multiple material layers.
3Productivity
If wafer bonding is used to stack transistors over memory structures, then integration efficiency and device density are improved, but material compatibility challenges increase
Solution Approach 1:
The wafer bonding process joins semiconductor wafers with matching material compositions and thermal expansion properties. By ensuring homogeneity in material selection for stacked transistor and memory structures, the bonding interface achieves reliable mechanical and thermal compatibility, enabling efficient integration while maintaining material compatibility across the stacked device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient integration of nano-structure transistors and memory structures, enhancing device density and performance by addressing etch selectivity and material compatibility issues, thereby improving the fabrication of GAA transistors.
Implementation Method 1
with a wafer bonding process to stack transistors over memory structures
Data Source
AI summary
A semiconductor structure and method for forming the semiconductor are provided. The semiconductor structure includes a first electrode comprising a first portion, a second portion, and a sheet portion connecting the first portion to the second portion. A ferroelectric material is over the sheet portion. A second electrode is over the ferroelectric material.