Ferroelectric Gain Memory Cell for Refresh-Free Data Retention
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Solution Overview
Problem
Memory cells with transistors suffer from leakage currents that reduce retention time, necessitating frequent refresh operations and complicating read and write operations.
Innovation Solution
Incorporating a ferroelectric material to store logic states via capacitance rather than voltage, making the memory cell non-volatile and enabling intrinsic amplification without the need for refresh or amplification circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a transistor is used to store logic states via voltage, then the memory cell can be read and written, but leakage currents reduce retention time and require frequent refresh operations
Solution Approach 1:
The patent changes the fundamental parameter for storing logic states from voltage (in volatile memory) to capacitance (in ferroelectric material). This parameter change eliminates the leakage current issue because capacitance storage in ferroelectric material does not suffer from the same leakage problems as voltage storage in transistors, thereby achieving non-volatile storage without refresh operations
Solution Approach 2:
The patent replaces the electrical voltage-based storage mechanism with a capacitance-based storage mechanism using ferroelectric material. This substitution fundamentally changes how logic states are maintained, replacing the transient voltage hold with stable capacitance storage that persists without power, eliminating the need for refresh operations
2Duration of action of stationary object
If refresh operations are implemented to maintain logic states, then retention time is extended, but system complexity and power consumption increase
Solution Approach 1:
The ferroelectric material inherently maintains its capacitance state without requiring external refresh operations. The material's ferroelectric properties enable it to self-maintain the stored logic state indefinitely without intervention from refresh circuitry, thereby eliminating the need for complex refresh mechanisms and associated power consumption
3Measurement precision
If amplification circuitry is added to compensate for signal weakness, then read accuracy improves, but device complexity increases
Solution Approach 1:
The patent converts the typically harmful leakage current into a beneficial effect by using the transistor's channel as an inherent amplifier. The leakage current that would normally degrade the signal is instead harnessed to provide signal amplification during read operations, eliminating the need for separate amplification circuitry while improving read accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for long-term storage of logic states without refresh, supports non-destructive reads, and reduces the complexity of memory systems by eliminating the need for refresh and amplification components.
Implementation Method 1
a ferroelectric material coupled with the first transistor and a plate line, and configured to have a capacitance that is based at least in part on a voltage difference between the plate line and the digit line
Implementation Method 2
the capacitance of the ferroelectric material is based at least in part on the voltage difference and is representative of the logic state
Data Source
AI summary
Methods, systems, and devices for a non-volatile gain memory cell are described. The memory cell may include a first transistor coupled with a digit line and comprising a gate terminal coupled with a word line, a ferroelectric material coupled with the first transistor and a plate line, a second transistor coupled with the plate line, and a third transistor coupled with the second transistor and the digit line. The second transistor including a gate terminal coupled with a node between the ferroelectric material and the first transistor. The third transistor including a gate terminal coupled with the word line.